參數(shù)資料
型號(hào): AD5724RBREZ
廠商: Analog Devices Inc
文件頁數(shù): 19/32頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DSP/SRL 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 10µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 310mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
AD5724R/AD5734R/AD5754R
Rev. E | Page 26 of 32
INPUT REGISTER
The input register is 24 bits wide and consists of a read/write bit (R/W), a reserved bit (zero) which must always be set to 0, three register
select bits (REG1, REG2, REG3), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB first on
the SDIN pin.
shows the register format, while
describes the function of each bit in the register. All registers are read/
write registers.
Table 17. AD5754R Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB0
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
Data
Table 18. Input Register Bit Functions
Data
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits to determine if a write operation is to the DAC register, output range
select register, power control register, or control register
REG2
REG1
REG0
Function
0
DAC register
0
1
Output range select register
0
1
0
Power control register
0
1
Control register
A2, A1, A0
These bits are used to decode the DAC channels
A2
A1
A0
Channel Address
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
1
0
All four DACs
DB15 to DB0
Data bits
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