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| 型號： | AD5641BKS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.7 V to 5.5 V, <100 uA, 14-Bit nanoDAC D/A in SC70 Package |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PDSO6 |
| 封裝： | PLASTIC, SC-70, MO-203AB, SURFACE MOUNT PACKAGE-6 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 572K |
| 代理商： | AD5641BKS |
AD5641
Preliminary Technical Data
GENERAL DESCRIPTION
D/A SECTION
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 24 is a block diagram of the DAC
architecture.
Rev. PrC | Page 12 of 20
V
DD
V
OUT
GND
RESISTOR
NETWORK
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
0
Figure 24. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
×
=
16384
D
V
V
DD
OUT
where
D
is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
RESISTOR STRING
The resistor string section is shown in Figure 25. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
0
Figure 25. Resistor String Section
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
DD
. It is
capable of driving a load of 2 k in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 10. The slew rate is 0.5 V/μs, with a half-
scale settling time of 8 μs with the output unloaded.
SERIAL INTERFACE
The AD5641 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5641compatible with high speed
DSPs. On the 16
th
falling clock edge, the last data bit is clocked
in and the programmed function is executed (a change in DAC
register contents and/or a change in the mode of operation). At
this stage, the SYNC line might be kept low or brought high. In
either case, it must be brought high for a minimum of 33 ns
before the next write sequence so that a falling edge of SYNC
can initiate the next write sequence.
Because the SYNC buffer draws more current when V
IN
= 1.8 V
than it does when V
IN
= 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part, as mentioned above. However, it must be brought high
again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 26). The first
two bits are control bits that determine the part’s mode of
operation (normal mode or any one of three power-down
modes). For a complete description of the various modes, see
the Power-Down Modes section. The next 16 bits are the data
bits, which are transferred to the DAC register on the 16
th
falling
edge of SCLK.
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
1 k
TO GND
100 k
TO GND
THREE-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
0
Figure 26. Input Register Contents
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