VOUT 1 7 V
參數(shù)資料
型號(hào): AD5626BRMZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 0K
描述: IC DAC NANO 12BIT 8-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: nanoDAC™
設(shè)置時(shí)間: 16µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 12.5mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
其它名稱: AD5626BRMZ-REEL7DKR
AD5626
Rev. A | Page 14 of 20
CS
CLR
SCLK
LDAC
SDIN
2
8
6
5
3
4
VOUT
1
7
VDD
GND
AD5626
0.1F
10F
+5V
+
A2
8
4
5
7
6
R1
10k
R2
12.7k
P1
10k
R3
247k
2.5V
TRIM
ZERO-SCALE
ADJUST
–2.5V
–5V
–5V ≤ VO ≤ +5V
+
R4
23.7k
FULL-SCALE
ADJUST
P3
500
P2
10k
A1
3
1
2
100
A1, A2 = 1/2 OP295
–2.5V
+
+5V
0.1F
ADR03
2
4
6
5
0.01F
06
75
7
-03
0
Figure 30. Bipolar Output Operation
06
75
7-
0
31
CS
CLR
SCLK
LDAC
SDIN
2
8
6
5
3
4
VOUT
1
7
VDD
GND
AD5626
+5V
0.1F
+5V
+2.5V
A1
8
4
3
1
2
R3
R4
–5V
VO
+
R2
+5V
0.1F
ADR03
2
4
6
R1
±2.5V
±5V
15k + 274
R1
10k
43.2k + 499
10k
20k
R2
10k
R3
R4
VOUTRANGE
A1 = 1/2 OP295
Figure 31. Bipolar Output Operation Without Trim
Table 7. Bipolar Code
Hexadecimal Number
in DAC Register
Decimal Number
in DAC Register
Analog Output
Voltage (V)
FFF
4095
4.9976
801
2049
2.44E 3
800
2048
0
7FF
2047
+2.44E 3
000
0
+5
To maintain monotonicity and accuracy, R1, R2, and R4 should
be selected to match within 0.01% and must all be of the same
(preferably metal foil) type to assure temperature coefficient
matching. Mismatching between R1 and R2 causes offset and
gain errors whereas an R4 to R1 or R4 to R2 mismatch yields
gain errors.
For applications that do not require high accuracy, the circuit
illustrated in Figure 31 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim. The output
voltage is coded in offset binary and is given by
R1
R2
R1
R2
R4
R3
R4
Code
Digital
V
O
×
+
×
+
×
=
5
.
2
1
mV
1
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