參數(shù)資料
型號: AD5583YRVZ
廠商: Analog Devices Inc
文件頁數(shù): 9/20頁
文件大?。?/td> 0K
描述: IC DAC 10BIT QUAD VOUT 48-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 39
設(shè)置時間: 5µs
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 30mW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 200k
產(chǎn)品目錄頁面: 783 (CN2011-ZH PDF)
REV. A
AD5582/AD5583
–17–
compliance is mainly limited by the op amp supply voltages.
This circuit can be used in 4 to 20 mA current transmitters with
up to 500
W of load.
U4
AD8510
+
R3'
50
R3
50
C1
10pF
R2
15k
R2'
15k
R1'
150k
VL
IL
LOAD
R1
150k
U2
AD5582
VREFH
R1
RCT
R2
VREFL
OP1177
+
+5V
VDD
VSS
U1
ADR421
+2.5V
–2.5V
DECOUPLING CAPS ARE OMITTED FOR CLARITY
–5V
+5V
–5V
+15V
–15V
VDAC
Figure 6. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities
Figure 6 shows that if the resistor network is matched, the load
current is:
I
RR
R
V
L
DAC
=
+
()
23
1
3
/
(4)
R3 in theory can be made small to achieve the current needed
within the U4 output current driving capability. In this circuit,
the AD8510 can deliver
±20 mA in both directions and the
voltage compliance approaches
±15 V.
This circuit is versatile, but users must pay attention to the
compensation. Without C1, it can be shown that the output
impedance becomes:
Z
RR R
R
RR
R
O
=
+
()
+
()
+
()
13
1
2
12
3
1
2
3
'
'' –
'
(5)
If the resistors are perfectly matched, ZO is infinite, which is
highly desirable. On the other hand, if they are not matched, ZO
can either be positive or negative. The latter, because of the
pole in the right S-plane, can cause oscillation. As a result, C1
in the range of a few pF is needed to prevent the oscillation. For
critical applications, C1 should be found empirically without
overcompensating.
Boosted Programmable Voltage Source
For users who need higher than 20 mA current driving capabil-
ity, they can add an external op amp and power transistors. The
capacitive loading capability will change, but it can still drive
100 nF capacitive load without oscillation in this circuit. Figure 7
shows a programmable power supply with 200 mA capability.
U3
OP1177
+
U1
REF198
VDD
C1
1 F
+4.096V
+5V
U2
AD5582
VREFH
VREFL
VDD
VSS
+15V
FDV30IN
N1
LOAD
VO
DECOUPLING CAPS ARE OMITTED FOR CLARITY
Figure 7. Boosted Programmable Voltage Source
Table I. AD5582/AD5583 Logic Table
INPUT
DAC
OPERATION
SELECTED
A1
A0
R/
WCS
LDAC
RS
REGISTER
MODE
DAC
00
01
Write
Transparent
A
01
00
01
Write
Transparent
B
10
00
01
Write
Transparent
C
11
00
01
Write
Transparent
D
00
11
Write
Hold
Write Input
A
01
00
11
Write
Hold
Write Input
B
10
00
11
Write
Hold
Write Input
C
11
00
11
Write
Hold
Write Input
D
00
10
11
Read
Hold
Readback to D0 to DN
A
01
10
11
Read
Hold
Readback to D0 to DN
B
10
11
Read
Hold
Readback to D0 to DN
C
11
10
11
Read
Hold
Readback to D0 to DN
D
XX
X1
01
Hold
Update All Registers
All
XX
X
1
Hold
All
XX
X0
All registers reset to midscale or zero scale.
All
XX
X
1
X
All registers latched to midscale or zero scale.
All
MSB = 0 resets to zero scale, MSB = 1 resets to midscale. X: Don’t Care. Input and output registers are transparent when asserted.
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