VOUT 1
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      參數(shù)資料
      型號(hào): AD5551BRZ
      廠商: Analog Devices Inc
      文件頁(yè)數(shù): 13/16頁(yè)
      文件大?。?/td> 0K
      描述: IC DAC 14BIT SERIAL-IN 8-SOIC
      產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
      DAC Architectures
      標(biāo)準(zhǔn)包裝: 1
      設(shè)置時(shí)間: 1µs
      位數(shù): 14
      數(shù)據(jù)接口: 串行
      轉(zhuǎn)換器數(shù)目: 1
      電壓電源: 單電源
      功率耗散(最大): 6.05mW
      工作溫度: -40°C ~ 85°C
      安裝類型: 表面貼裝
      封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
      供應(yīng)商設(shè)備封裝: 8-SOIC
      包裝: 管件
      輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
      采樣率(每秒): 1M
      產(chǎn)品目錄頁(yè)面: 783 (CN2011-ZH PDF)
      AD5551/AD5552
      Rev. A | Page 6 of 16
      PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
      VOUT 1
      AGND 2
      VREF 3
      CS 4
      VDD
      8
      DGND
      7
      DIN
      6
      SCLK
      5
      AD5551
      TOP VIEW
      (Not to Scale)
      01
      94
      3-
      0
      04
      Figure 4. AD5551 Pin Configuration
      RFB 1
      VOUT 2
      AGNDF 3
      AGNDS 4
      VDD
      14
      INV
      13
      DGND
      12
      LDAC
      11
      VREFS 5
      DIN
      10
      VREFF 6
      NC
      9
      CS 7
      SCLK
      8
      AD5552
      TOP VIEW
      (Not to Scale)
      NC = NO CONNECNT
      01
      94
      3-
      0
      05
      Figure 5. AD5552 Pin Configuration
      Table 4. AD5551 Pin Function Descriptions
      Pin No.
      Mnemonic
      Description
      1
      VOUT
      Analog Output Voltage from the DAC.
      2
      AGND
      Ground Reference Point for Analog Circuitry.
      3
      VREF
      This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD.
      4
      CS
      This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
      5
      SCLK
      Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
      and 60%.
      6
      DIN
      Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
      7
      DGND
      Digital Ground. Ground reference for digital circuitry.
      8
      VDD
      Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.
      Table 5. AD5552 Pin Function Descriptions
      Pin No.
      Mnemonic
      Description
      1
      RFB
      Feedback Resistor. In bipolar mode, connect this pin to external op amp output.
      2
      VOUT
      Analog Output Voltage from the DAC.
      3
      AGNDF
      Ground Reference Point for Analog Circuitry (Force).
      4
      AGNDS
      Ground Reference Point for Analog Circuitry (Sense).
      5
      VREFS
      This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD.
      6
      VREFF
      This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD.
      7
      CS
      This is an active low-logic input signal. The chip select signal is used to frame the serial data input.
      8
      SCLK
      Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
      and 60%.
      9
      NC
      No Connect.
      10
      DIN
      Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK.
      11
      LDAC
      LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
      input register.
      12
      DGND
      Digital Ground. Ground reference for digital circuitry.
      13
      INV
      Connected to the internal scaling resistors of the DAC. Connect the INV pin to external op amps inverting input in
      bipolar mode.
      14
      VDD
      Analog Supply Voltage, 2.7 V to 5.5 V ± 10%.
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