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參數(shù)資料
| 型號： | AD5512AACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 16LFCSP |
| 標(biāo)準包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6.05mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP |
| 包裝： | 標(biāo)準包裝 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5512AACPZ-REEL7DKR |
AD5512A/AD5542A
Rev. A | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
09199-
036
12
11
10
1
3
4
DGND
LDAC
CLR
9
DIN
VOUT
AGNDS
2
AGNDF
REFS
6
CS
5
RE
F
7
NC
8
S
CL
K
16
R
FB
15
V
DD
14
V
L
OGIC
13
INV
TOP
VIEW
NC = NO CONNECT
(Not to Scale)
Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration
1
REF
2
CS
3
SCLK
4
DIN
5
CLR
10 GND
9
VDD
8
RFB
7
INV
6
VOUT
09199-
034
AD5542A-1
TOP VIEW
Not to Scale
NOTES
1. THE EXPOSED PADDLE SHOULD BE
TIED TO THE POINT OF LOWEST
POTENTIAL, IN THIS CASE, GND.
Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration
Table 7. AD5512A/AD5542A Pin Function Descriptions
Pin No.
16-Lead
LFCSP
10-Lead
LFCSP
Mnemonic
Description
1
6
V
OUT
Analog Output Voltage from the DAC.
2
AGNDF
Ground Reference Point for Analog Circuitry (Force).
3
AGNDS
Ground Reference Point for Analog Circuitry (Sense).
4
REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
DD.
5
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to V
DD.
6
2
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
7
NC
No Connect.
8
3
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be
between 40% and 60%.
9
4
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the
rising edge of SCLK.
10
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses
are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale.
11
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the
contents of the input register.
12
DGND
Digital Ground. Ground reference for digital circuitry.
13
7
INV
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op
amps inverting input in bipolar mode.
14
V
LOGIC
Logic Power Supply.
15
9
V
DD
Analog Supply Voltage, 5 V ± 10%.
16
8
R
FB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
1
REF
Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can
range from 2 V to V
DD.
10
GND
Ground.
EPAD
Exposed Pad
The exposed pad should be tied to the point of lowest potential, in this case, GND.
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