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參數(shù)資料
| 型號(hào)： | AD5447YRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 80ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 3.3µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 21.3M |
| 配用： | EVAL-AD5447EBZ-ND - BOARD EVALUATION FOR AD5447 |
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AD5428/AD5440/AD5447
Data Sheet
Rev. C | Page 20 of 32
REFERENCE SELECTION
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature
coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range
0° to 50°C dictates that the maximum system drift with temp-
erature should be less than 78 ppm/°C. A 12-bit system with the
same temperature range to overall specification within 2 LSBs
requires a maximum drift of 10 ppm/°C. Choosing a precision
reference with low output temperature coefficient minimizes this
error source. Table 9 lists some references available from Analog
Devices that are suitable for use with these current output DACs.
Current-steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
For D = 1 2n, the output voltage is
()n
IN
OUT
V
D
V
=
=
2
1
/
VOUT
VDD
GND
VIN
AGND
IOUTA
RFBA VDD
VREFA
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
04462-040
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. Because of the code-dependent output resistance of the
DAC, the input offset voltage of an op amp is multiplied by the
variable gain of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input offset voltage should be <1/4 LSB
to ensure monotonic behavior when stepping through codes.
Figure 43. Current-Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (0001 0000)—that is, 16 decimal—in the circuit of
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have a weight in the range of 15.5/256 to 16.5/256 so that the
possible output voltage is in the range of 15.5 VIN to 16.5 VIN—
an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage-
switching circuits, because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-
switching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (the voltage output node
in this application) of the DAC by using low input capacitance
buffer amplifiers and careful board design.
Output Error Voltage Due to DAC Leakage
(
) D
R
Leakage
/
×
=
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide variety of single-
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