I
參數(shù)資料
型號: AD5446YRMZ
廠商: Analog Devices Inc
文件頁數(shù): 28/29頁
文件大?。?/td> 0K
描述: IC DAC 14BIT MULTIPLYING 10-MSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計資源: Versatile High Precision Programmable Current Sources Using DACs, Op Amps, and MOSFET Transistors (CN0151)
標(biāo)準(zhǔn)包裝: 50
位數(shù): 14
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 50.5µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 2.7M
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
配用: EVAL-AD5446EBZ-ND - BOARD EVALUATION FOR AD5446
Data Sheet
AD5444/AD5446
Rev. E | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04588-
005
10
9
8
7
6
1
2
3
4
5
IOUT1
IOUT2
GND
SCLK
SDIN
RFB
VREF
VDD
SDO
AD5444/
AD5446
TOP VIEW
(Not to Scale)
SYNC
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
IOUT1
DAC Current Output.
2
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
GND
Ground Pin.
4
SCLK
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked
into the shift register on the rising edge of SCLK.
5
SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.
By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow
the user to change the active edge to the rising edge.
6
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low,
data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising
edge of SYNC.
7
SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to data loaded to the shift register.
8
VDD
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
9
VREF
DAC Reference Voltage Input.
10
RFB
DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.
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