參數(shù)資料
型號： AD5421CREZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 23/36頁
文件大?。?/td> 0K
描述： IC DAC 16BIT SPI/SRL 28TSSOP
標準包裝： 2,500
設置時間： 50µs
位數(shù)： 16
數(shù)據(jù)接口： 串行，SPI?
轉換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 625mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.173"，4.40mm 寬）裸露焊盤
供應商設備封裝： 28-TSSOP 裸露焊盤
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： *
Data Sheet
AD5421
Rev. G | Page 3 of 36
REVISION HISTORY
10/13—Rev. F to Rev. G
Added Figure 4; Renumbered Sequentially .................................10
Change to Table 7............................................................................11
Changes to Fault Alerts Section ....................................................21
Added Table 11; Renumbered Sequentially.................................24
Moved Figure 48..............................................................................25
Changes to Applications Information Section ............................32
Changes to Figure 51 ......................................................................33
1/13—Rev. E to Rev. F
Moved Revision History Section.....................................................3
Change to Table 7............................................................................11
Changes to Table 8 ..........................................................................13
Changes to On-Chip ADC Section...............................................23
Changes to Table 19 and On-Chip ADC Transfer Function
Equations Section............................................................................29
7/12—Rev. D to Rev. E
Changes to Figure 1 and Companion Products Section ..............1
Changes to Pin LOOP Description ............................................12
Changes to Applications Information Section and Figure 49 ...31
Added Figure 50 ..............................................................................32
5/12—Rev. C to Rev. D
Changes to Features Section and Applications Section; Added
Companion Products Section..........................................................1
Changes to Line Regulation Parameter, Table 1............................5
Updated Outline Dimensions........................................................33
12/11—Rev. B to Rev. C
Change to REFOUT1 Pin, Capacitive Load Parameter, Test
Conditions, Table 1 ...........................................................................4
Change to REGOUT Output, Capacitive Load Parameter, Test
Conditions, Table 1 ...........................................................................5
Changes to ESD Parameter, Table 6..............................................10
12/11—Rev. A to Rev. B
Added 32-Lead LFCSP ...................................................... Universal
Changes to the Specifications Section, Table 1 .............................3
Changes to Table 7 ..........................................................................10
Added Figure 5, Renumbered Sequentially.................................11
Changes to Table 8 ..........................................................................11
Changes to Figure 33 ......................................................................17
Changes to the On-Chip ADC Section........................................22
Changes to Figure 46 ......................................................................23
Changes to Figure 48 ......................................................................24
Changes to the Register Readback Section..................................25
Updated Outline Dimensions........................................................33
Changes to Ordering Guide...........................................................34
5/11—Rev. 0 to Rev. A
Changes to REGIN, REFOUT1, and REFOUT2 Pin Descriptions
in Table 8 ..........................................................................................10
Change to Figure 45........................................................................22
Changes to Input Shift Register Section, Table 11, and Register
Readback Section ............................................................................24
Changes to Figure 48 ......................................................................30
2/11—Revision 0: Initial Version
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