參數(shù)資料
型號(hào)： AD539KNZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/21頁(yè)
文件大?。?/td> 0K
描述： IC MULT/DIV DUAL CH LIN 16-DIP
標(biāo)準(zhǔn)包裝： 1
功能： 模擬乘法器/除法器
位元/級(jí)數(shù)： 雙象限
封裝/外殼： 16-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 16-PDIP
包裝： 管件
AD539
Rev. B | Page 14 of 20
Differential Configurations
When only one signal channel must be handled, it is often
advantageous to use the channels differentially. By subtracting
the Channel 1 and Channel 2 outputs, any residual transient
control feedthrough is virtually eliminated. Figure 22 shows a
minimal configuration where it is assumed that the host system
uses differential signals and a 50 Ω environment throughout.
This figure also shows a recommended control feedforward
network to improve large-signal response time. The control
feedthrough glitch is shown in Figure 12, where the input was
applied to Channel 1 and only the output of Channel 1 was
displayed on the oscilloscope. The improvement obtained when
CH1 and CH2 outputs are viewed differentially is clear in
Figure 13. The envelope rise time is of the order of 40 ns.
096
79-
0
22
1
2
3
4
16
15
14
13
5
12
6
11
7
10
8
9
AD539
VX
HF COMP
VY1
+VS
–VS
VY2
CONTROL
INPUT
(VS)
CHAN1
INPUT
CHAN2
INPUT
COMMON
OUTPUT
COMMON
BASE
COMMON
W1
Z1
CHAN1
OUTPUT
CHAN1
OUTPUT
CHAN2
OUTPUT
CHAN2
OUTPUT
Z2
W2
5nF
150pF
0.1F
+5V
–5V
51
56
100
Figure 22. High Speed Differential Configuration
(16-Lead SBDIP and PDIP Shown)
Lower distortion results when Channel 1 and Channel 2 are
driven by complementary inputs and the outputs are utilized
differentially, using a circuit such as the one shown in Figure 23.
Resistors R1 and R2 minimize a secondary distortion mechanism
caused by a collector modulation effect in the controlled cascode
stages (see the Theory of Operation section) by keeping the
voltage swing at the outputs to an acceptable level and should
have a value in the range of 100 Ω to 1000 Ω. Figure 14 shows
the improvement in distortion over the standard configuration
(compare with Figure 5). Note that the Z nodes (Pin 10 and
Pin 15) are returned to the control input; this prevents the early
onset of output transistor saturation.
096
79-
0
23
1
2
3
4
16
15
14
13
5
12
6
11
7
10
8
9
AD539
VX
VW = VX (VY2 – VY1)
HF COMP
VY1
+VS
–VS
VY2
INPUT
COMMON
OUTPUT
COMMON
BASE
COMMON
W1
Z1
CHAN1
OUTPUT
CHAN2
OUTPUT
Z2
W2
CC = 3nF
VX
+VS
–VS
VY1
VY2
R1
R2
Figure 23. Low Distortion Differential Configuration
(16-Lead SBDIP and PDIP Shown)
Even lower distortion (0.01%, or 80 dB) has been measured
using two output op amps in a configuration similar to that
shown in Figure 20 connected as virtual ground current summers
(to prevent the modulation effect). Note that to generate the
difference output it is merely necessary to connect the output of
the Channel 1 op amp to the Z node of Channel 2. In this way,
the net input to the Channel 2 op amp is the difference signal,
and the low distortion resultant appears as its output.
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