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| 型號(hào)： | AD538BDZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MULT/DIV REALTIME ACU 18-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 模擬計(jì)算裝置 |
| 位元/級(jí)數(shù)： | 單象限 |
| 封裝/外殼： | 18-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-CDIP |
| 包裝： | 管件 |
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AD538
Rev. E | Page 12 of 16
TWO-QUADRANT DIVISION
The two-quadrant linear divider circuit illustrated in Figure 14
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage
to it. The offsetting scheme changes the divider’s transfer
function from
=
X
Z
O
V
10
to
(
)
+
=
+
=
+
=
X
Z
X
Z
X
Z
O
V
A
V
AV
V
10
A
10
1
V
10
V
10
where:
=
kΩ
25
kΩ
35
A
As long as the magnitude of the denominator input is equal
to or greater than the magnitude of the numerator input, the
circuit accepts bipolar numerator voltages. However, under
the conditions of a 0 V numerator input, the output would
incorrectly equal +14 V. The offset can be removed by connecting
the 10 V reference through Resistors R1 and R2 to the output
section’s summing Node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The potentiometer,
R2, adjusts out or corrects this offset, leaving the desired
transfer function of 10 V (VZ/VX).
25k
35k
R2
10k
R1
12.4k
25k
35k
100
25k
25k
ANTILOG
LOG
OUTPUT
ZERO
ADJUST
100
AD538
IY
A
D
IX
VX
C
IN4148
VY
8
1
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
IZ
VZ
VO
I
B
+10V
+2V
OUTPUT
VO = 10
FOR VX ≥ VZ
VZ
VX
10M
VOS
3.9M
1M
ADJ
68k
–1.2V
AD589
–VS
NUMERATOR
VZ
DENOMINATOR
VX
OPTIONAL
Z OFFSET TRIM
00959-
015
+15V
–15V
Figure 14. Two-Quadrant Division with 10 V Scaling
LOG RATIO OPERATION
Figure 15 shows the AD538 configured for computing the log
of the ratio of two input voltages (or currents). The output
signal from B is connected to the summing junction of the
output amplifier via two series resistors. The 90.9 Ω metal film
resistor effectively degrades the temperature coefficient of the
±3500 ppm/°C resistor to produce a 1.09 kΩ +3300 ppm/°C
equivalent value. In this configuration, the VY input must
be tied to some voltage less than zero (1.2 V in this case)
removing this input from the transfer function.
The 5 kΩ potentiometer controls the circuit’s scale factor
adjustment providing a +1 V per decade adjustment. The
output offset potentiometer should be set to provide a zero
output with VX = VZ = 1 V. The input VZ adjustment should
be set for an output of 3 V with VZ = l mV and VX = 1 V.
25k
1M
AD589
68k
5%
OPTIONAL
INPUT VOS
ADJUSTMENT
10M
–1.2V
–VS
25k
100
90.9
1%
1k
+3500
ppm/°C
25k
25k
ANTILOG
LOG
OUTPUT
100
48.7
AD538
IY
A
D
IX
VX
C
IN4148
VY
8
1
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
IZ
VZ
VO
I
+15V
–15V
B
+10V
+2V
00959-
016
OUTPUT
VX
INPUT
VZ
VX
5k
SCALE
FACTOR
ADJUST
OPTIONAL
OUTPUT VOS
ADJUSTMENT
2k
1%
+VS
–VS
10k
10M
VO = 1V LOG10
Figure 15. Log Ratio Circuit
The log ratio circuit shown achieves ±0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction
at the input of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (that is, 1 V × log10 (1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
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