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參數(shù)資料
| 型號： | AD538ADZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 0K |
| 描述： | IC REALTIME ACU UNIT 18-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 模擬計(jì)算裝置 |
| 位元/級數(shù)： | 單象限 |
| 封裝/外殼： | 18-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 18-CDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 789 (CN2011-ZH PDF) |
AD538
Rev. E | Page 10 of 16
FUNCTIONAL DESCRIPTION
connect directly to the input log ratio amplifiers of the AD538.
This subsection provides an output voltage proportional to the
natural log of input voltage, VZ, minus the natural log of input
voltage, VX. The output of the log ratio subsection at B can be
expressed by the transfer function
=
X
Z
B
V
q
kT
V
ln
where:
k is 1.3806 × 1023 J/K.
q is 1.60219 × 1019 C.
T is in Kelvins.
The log ratio configuration may be used alone, if correctly
temperature compensated and scaled to the desired output
level (see the Applications Information section).
Under normal operation, the log-ratio output will be directly
connected to a second functional block at Input C, the antilog
subsection. This section performs the antilog according to the
transfer function:
=
kT
q
V
e
V
C
Y
O
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
VO = VYe
C
B
V
kT
q
Q
kT
V
X
Z
=
;
ln
which reduces to:
=
X
Z
Y
O
V
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity VZ/VX to the mth power. Without external
programming, m is unity. Thus, the overall AD538 transfer
function equals:
m
X
Z
Y
O
V
=
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the VY input can
be used to multiply the ratio VZ/VX by a convenient scale factor.
The actual multiplication by the VY input signal is accomplished
by adding the log of the VY input signal to the signal at C, which
is already in the log domain.
STABILITY PRECAUTIONS
At higher frequencies, the multistaged signal path of the AD538
can result in large phase shifts (as illustrated in Figure 11). If a
condition of high incremental gain exists along that path (for
example, VO = VY × VZ/VX = 10 V × 10 mV/10 mV = 10 V so
that ΔVO/ΔVX = 1000), then small amounts of capacitive feedback
from VO to the current inputs IZ or IX can result in instability.
Appropriate care should be exercised in board layout to prevent
capacitive feedback mechanisms under these conditions.
00959-
012
LOGe
IY
VY
Ln Y
LOGe
IZ
VZ
Ln Z
LOGe
IX
VX
Ln X
Σ
BUFFER
+
–
Ln Z – Ln X
M(Ln Z – Ln X)
M(Ln Z – Ln X) +Ln Y
ANTILOGe
0.2
≤M≤5
VO = VY
VZ
VX
M
Figure 11. Model Circuit
USING THE VOLTAGE REFERENCES
A stable band gap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage output of
+10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages
between +2 V and +10.2 V buffered as shown in Figure 12. The
output impedance at Pin 5 is approximately 5 kΩ. Note that any
loading of this pin produces an error in the +10 V reference
voltage. External loads on the +2 V output should be greater
than 500 kΩ to maintain errors less than 1%.
25k
25k
100
25k
25k
ANTILOG
LOG
OUTPUT
100
50k
+2V TO +10.2V
BUFFERED
11.5k
AD538
IY
A
D
IX
VX
C
VY
8
1
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
IZ
VZ
VO
I
+VS
–VS
B
REF OUT
+2V
00959-
013
Figure 12. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pin 4 and Pin 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
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