參數(shù)資料
型號: AD5384BBC-3REEL7
廠商: Analog Devices Inc
文件頁數(shù): 20/32頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 40CH 3V 100-CSPBGA
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5384 Models Discontinuation 15/May/2012
標(biāo)準(zhǔn)包裝: 400
設(shè)置時(shí)間: 8µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 單電源
功率耗散(最大): 80mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 100-CSBGA(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 40 電壓,單極
采樣率(每秒): 125k
Data Sheet
AD5384
3-Byte Mode
In 3-byte mode, the user can update more than one channel in a
write sequence without having to write the device address byte
each time. The device address byte is required only once; sub-
sequent channel updates require the pointer byte and the data
bytes. In 3-byte mode, the use must begin with an address byte
(R/W = 0), after which the DAC acknowledges that it is prepared
to receive data by pulling SDA low. The address byte is followed
by the pointer byte. This addresses the specific channel in the
DAC to be addressed and also is acknowledged by the DAC.
This is then followed by the two data bytes, REG1 and REG0,
which determine the register to be updated.
If a stop condition does not follow the data bytes, another
channel can be updated by sending a new pointer byte, followed
by the data bytes. This mode requires only three bytes to be sent
to update any channel once the device is initially addressed, and
it reduces the software overhead in updating the AD5384 channels.
A stop condition at any time exits this mode. Figure 28 shows a
typical configuration.
SCL
SDA
SCL
SDA
SCL
SDA
SCL
START COND
BY MASTER
ACK BY
AD538x
MSB
ADDRESS BYTE
POINTER BYTE FOR CHANNEL N
MOST SIGNIFICANT DATA BYTE
POINTER BYTE FOR CHANNEL NEXT CHANNEL
LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
ACK BY
AD538x
ACK BY
AD538x
DATA FOR CHANNEL N
DATA FOR CHANNEL NEXT CHANNEL
ACK BY
AD538x
1
0
A5
A4
A3
A2
A1
A0
0
1
0
A5
A4
A3
A2
A1
A0
1
AD1
AD0
R/W
REG1
REG0
MSB
LSB
MSB
LSB
MSB
ACK BY
AD538x
ACK BY
AD538x
ACK BY
AD538x
STOP COND
BY MASTER
REG1
REG0
MSB
LSB
MSB
LSB
04652-
030
Figure 28. 3-Byte, I2C Write Operation
Rev. B | Page 27 of 32
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