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| 型號(hào)： | AD5380BST-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100 |
| 封裝： | 14 X 14 MM, MS-026BED, LQFP-100 |
| 文件頁(yè)數(shù)： | 6/34頁(yè) |
| 文件大?。?/td> | 975K |
| 代理商： | AD5380BST-5 |
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PRELIMINARY TECHNICAL DATA
REV. PrF 09/2003
–6–
SERIAL INTERFACE
Parameter
1,2,3
Limit at T
MIN,
T
MAX
Units
Description
t
1
t
2
t
3
t
4
33
13
13
13
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC
Falling Edge to SCLK Falling Edge Setup
Time
24th SCLK Falling Edge to
SYNC
Falling Edge
Minimum
SYNC
Low Time
Minimum
SYNC
High Time
Minimum
SYNC
High Time in Readback Mode
Data Setup Time
Data Hold Time
24th SCLK Falling Edge to
BUSY
Falling Edge
BUSY
Pulse Width Low (Single Channel Update)
24th SCLK Falling Edge to
LDAC
Falling Edge
LDAC
Pulse Width Low
BUSY
Rising Edge to DAC Output Response Time
BUSY
Rising Edge to
LDAC
Falling Edge
LDAC
Falling Edge to
DAC Output Response Time
DAC Output Settling Time, Boost Mode off.
CLR
Pulse Width Low
CLR
Pulse Activation Time
SCLK Rising Edge to SDO Valid
SCLK Falling Edge to
SYNC
Rising Edge
SYNC
Rising Edge to SCLK Rising Edge
SYNC
Rising Edge to
LDAC
Falling Edge
t
54
t
64
t
7
t
7A
t
8
t
t
9
t
t
11
t
13
t
14
t
15
t
16
t
17
t
18
t
t
19
t
217
t
227
t
237
13
33
10
50
5
4.5
30
900
20
20
100
0
100
8
20
12
20
5
8
20
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns min
ns min
ns max
ns min
ns min
μs typ
ns min
μs max
ns max
ns min
ns min
ns min
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figures 3 and 4
4
Stand-Alone Mode only.
5
This is measured with the load circuit of Figure 1a.
6
This is measured with the load circuit of Figure 1b.
7
Daisy-Chain Mode only.
Specifications subject to change without notice.
(DV
DD
= 2.7V to 5.5V ; AV
DD
=+4.5V to +5.5V or +2.7V to +3.6V; AGND= DGND = 0 V; )
All specifications T
MIN
to T
MAX
unless otherwise noted.)
TIMING CHARACTERISTICS
I
OL
200uA
I
OH
200uA
C
50pF
TO
OUTPUT
PIN
VOH (MIN) or
VOL (MAX)
C
50pF
R
2.2k
TO
OUTPUT
PIN
VOL
VCC
Figure 1a Load Circuit for
BUSY
Timing Diagram
Figure 1b. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain mode)
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