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參數(shù)資料
| 型號： | AD5348BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 14-bit 65MSPS ADC with serialized LVDS Output 48-VQFN -40 to 85 |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 949K |
| 代理商： | AD5348BCP |
AD5346/AD5347/AD5348
AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 24
TOP VIEW
(Not to Scale)
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
AD5348
LDAC
A1
A0
WR
CS
DB
11
DB
10
DB
9
AGND
V
OUT
D
V
REF
CD
V
REF
EF
V
REF
GH
V
OUT
C
V
OUT
B
V
OUT
A
V
REF
AB
PD
V
DD
DB
4
DB
3
DB
5
DB
6
CLR
GAIN
DB
7
DB
8
12-BIT
V
OUT
H
DGND
V
OUT
G
V
OUT
F
V
OUT
E
A2
RD
BUF
DB
2
DB
1
DB
0
0
Figure 9. AD5348 Pin Configuration—TSSOP
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
L
A
A
W
CS
AGND
V
OUT
D
V
R
C
V
R
E
V
R
G
V
OUT
C
V
OUT
B
V
OUT
A
V
R
A
P
V
D
DB
4
DB
5
DB
6
C
G
DB
11
DB
10
DB
7
DB
8
DB
9
V
OUT
H
V
OUT
G
V
OUT
F
V
OUT
E
D
A
RD
B
AGND
V
D
TOP VIEW
(Not to Scale)
AD5348
12-BIT
D
3
D
2
D
1
D
0
0
Figure 10. AD5348 Pin Configuration—LFCSP
Table 7. AD5348 Pin Function Descriptions
Pin Number
TSSOP
LFCSP
Mnemonic
1
35
V
REF
GH
2
36
V
REF
EF
3
37
V
REF
CD
4
38, 39
V
DD
Function
Reference Input for DACs G and H.
Reference Input for DACs E and F.
Reference Input for DACs C and D.
Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND. Both V
DD
pins on the LFCSP package must be at
the same potential.
Reference Input for DACs A and B.
Output of DAC X. Buffered output with rail-to-rail operation.
5
6–9,
11–14
10
15
16
17
40
1–4,
7–10
5, 6
11
12
13
V
REF
AB
V
OUT
X
AGND
DGND
BUF
LDAC
Analog Ground. Ground reference for analog circuitry.
Digital Ground. Ground reference for digital circuitry.
Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows
all DAC outputs to be simultaneously updated.
LSB Address Pin. Selects which DAC is to be written to.
Address Pin. Selects which DAC is to be written to.
MSB Address Pin. Selects which DAC is to be written to.
Twelve Parallel Data Inputs. DB
11
is the MSB of these 12 bits.
Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with
RD to read back data from a DAC.
Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.
Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
REF
or 0 V to 2 × V
REF
.
Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
18
19
20
21–32
33
14
15
16
17–28
29
A0
A1
A2
DB
0
–DB
11
CS
34
35
36
37
38
30
31
32
33
34
RD
WR
GAIN
CLR
PD
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