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參數(shù)資料
| 型號(hào)： | AD5346BCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 949K |
| 代理商： | AD5346BCP-REEL |
AD5346/AD5347/AD5348
Parameter
2
LOGIC OUTPUTS
6
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
Output High Voltage, V
OH
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
Rev. 0 | Page 4 of 24
B Version
1
Typ
Unit
V
V
V
V
V
mA
mA
Conditions/Comments
I
SINK
= 200 μA
I
SOURCE
= 200 μA
I
SINK
= 200 μA
I
SOURCE
= 200 μA
V
IH
= V
DD
, V
IL
= GND
All DACs in unbuffered mode. In buffered mode,
extra current is typically x μA per DAC, where x = 5 μA +
V
REF
/R
DAC
V
IH
= V
DD
, V
IL
= GND
Min
V
DD
– 1
V
DD
– 0.5
2.5
Max
0.4
0.4
5.5
1.65
1.4
1
0.8
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.5 V to 3.6 V
See footnotes after the AC Characteristics table.
AC CHARACTERISTICS
6
Table 2. V
DD
= 2.5 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted
B Version
1
Parameter
2
Min Typ
Max
Unit
Output Voltage Settling Time
AD5346
6
8
μs
AD5347
7
9
μs
AD5348
8
10
μs
Slew Rate
0.7
V/μs
Major Code Transition Glitch
Energy
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
1
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3.5
nV-s
Multiplying Bandwidth
200
kHz
Total Harmonic Distortion
–70
0.4
0.12
1
1
μA
μA
Conditions/Comments
V
REF
= 2 V
1/4 scale to 3/4 scale change (40 H to C0 H)
1/4 scale to 3/4 scale change (100 H to 300 H)
1/4 scale to 3/4 scale change (400 H to C00 H)
8
nV-s
1 LSB change around major carry
V
REF
= 2 V ±0.1 V p-p; unbuffered mode
V
REF
= 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode
1
Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.
2
See Terminology section.
3
Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
the offset plus gain error must be positive.
I
OH
I
OL
TO OUTPUT
PIN
V
OH
(min) + V
OL
(max)
2
C
L
50pF
200
μ
A
200
μ
A
0
Figure 2. Load Circuit for Digital Output Timing Specifications
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