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| 型號(hào)： | AD5316 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Rail-To-Rail,Voltage Output 10-Bit DACs(滿幅度電壓輸出雙10位D/A轉(zhuǎn)換器) |
| 中文描述： | 雙通道軌至軌電壓輸出10位DAC（滿幅度電壓輸出雙10位的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 351K |
| 代理商： | AD5316 |
2
3
AD5306/16/26 Prelim Technical Information
Prelim B 9/98
PRELMNARY
ns max
t
R
, Rise Time of both SCL and SDA when receiving
20 + 0.1C
b3
ns min
250
ns max
t
F
, Fall Time of SDA when transmitting.
300
ns max
t
F
, Fall Time of both SCL and SDA when receiving
20 + 0.1C
b3
ns min
400
pF max
Capacitive Load for Each Bus Line.
50
ns max
Pulse width of spike Suppressed.
Parameter
B Version
3
Min
Units
Conditions/Comments
Typ
Max
Output Voltage Settling Time
AD5306
4
μs
Full-Scale settling time. V
REF
= +2.5V. V
DD
= +5V.
Full-Scale settling time. V
REF
= +2.5V. V
DD
= +5V.
Full-Scale settling time. V
REF
= +2.5V. V
DD
= +5V.
AD5316
6
μs
AD5326
8
μs
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Power Supply Rejection Ratio
Output Noise Spectral Density
1
20
0.5
0.5
10
15
TBD
TBD
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
dB
nV/(Hz)
1/2
1 LSB change around major carry.
TBD
V
DD
= ±10%
TBD
AC CHARACTERISTICS
1,2
(V
DD
= +2.5V to +5.5 V; R
L
=2k
to GND; C
L
=200pFto GND; All specifica-
tions T
MIN
to T
MAX
unless otherwise noted.)
NOTES
1
See Terminology
2
Guaranteed by Design and Characterization, not production tested.
3
Temperature ranges are as follows: B Version: -40°C to +105°C.
Specifications subject to change without notice.
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Units
Conditions/Comments
F
SCL
t
1
t
2
t
3
t
4
t
t
5
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
SCL Clock Frequency
SCL Cycle Time
t
HIGH
, SCL High Time
t
LOW
, SCL Low Time
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
SU,DAT
, Data Setup Time
t
HD,DAT
, Data Hold Time
t
7
t
8
t
9
t
SU,STA
, Setup Time for Repeated Start
t
SU,STO
, Stop Condition Setup Time
t
BUF
, Bus Free Time Between a STOP Condition and a
t
10
300
t
11
t
11
C
b
t
SP
4
NOTES
1
See Figure 1.
2
A master device must provide a hold time of at least 300ns for the SDA signal (referred to the V
IH min
of the SCL signal) in order to bridge the unde-
fined region of SCL's falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3V
DD
and 0.7V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50ns.
TIMING CHARACTERISTICS
1
(V
DD
= +2.5 V to +5.5 V . All specifications T
MIN
to T
MAX
unless otherwise
noted)
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