參數(shù)資料
型號： AD5308BRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/28頁
文件大?。?/td> 0K
描述： IC DAC 8BIT OCTAL W/BUFF 16TSSOP
產品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 96
設置時間： 6µs
位數(shù)： 8
數(shù)據接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉換器數(shù)目： 8
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 8 電壓，單極；8 電壓，雙極
采樣率（每秒）： 167k
產品目錄頁面： 782 (CN2011-ZH PDF)
AD5308/AD5318/AD5328
Rev. F | Page 17 of 28
Control Functions
BUF
In the case of a control function, the MSB (Bit 15) is a 1. This is
followed by two control bits, which determine the mode. There
are four different control modes: reference and gain mode, LDAC
mode, power-down mode, and reset mode. The write sequences
for these modes are shown in
.
This controls whether the reference of a group of DACs is
buffered or unbuffered. The reference of the first group of DACs
(A, B, C, and D) is controlled by setting Bit 2, and the second
group of DACs (E, F, G, and H) is controlled by setting Bit 3.
0: unbuffered reference.
1: buffered reference.
Reference and Gain Mode
GAIN
This mode determines whether the reference for each group of
DACs is buffered, unbuffered, or from VDD. It also determines
the gain of the output amplifier. To set up the reference of both
groups, set the control bits to (00), set the GAIN bits, the BUF
bits, and the VDD bits.
The gain of the DACs is controlled by setting Bit 4 for the first
group of DACs (A, B, C, and D) and Bit 5 for the second group
of DACs (E, F, G, and H).
0: output range of 0 V to VREF.
1: output range of 0 V to 2 VREF.
Table 7. Control Words for the AD53x8
D/C
Control Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode
GAIN Bits
BUF Bits
VDD Bits
Gain of output amplifier and
1
0
x
E...H
A...D
E...H
A...D
E...H
A...D
reference selection
LDAC Bits
LDAC
1
0
1
x
1/0
Channels
1
0
x
H
G
F
E
D
C
B
A
Power-down
Reset
1
1/0
x
Reset
LDAC Mode
02812-031
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
BIT 0
(LSB)
BIT 15
(MSB)
DATA BITS
A1
A2
D/C
LDAC mode controls LDAC, which determines when data is
transferred from the input registers to the DAC registers. There
are three options when updating the DAC registers, as shown in
.
Figure 32. AD5308 Input Shift Register Contents
02812
-032
DATA BITS
A0
BIT 0
(LSB)
BIT 15
(MSB)
A1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
A2
D/C
Table 8. LDAC Mode
Bit 15
Bit 14
Bit 13
Bits 12:2
Bit 1
Bit 0
Description
LDAC low
1
0
1
x ... x
0
Figure 33. AD5318 Input Shift Register Contents
LDAC high
1
0
1
x ... x
0
1
02812
-033
DATA BITS
A0
BIT 0
(LSB)
BIT 15
(MSB)
A1
A2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D11
D/C
LDAC single
update
1
0
1
x ... x
1
0
1
0
1
x ... x
1
Reserved
Figure 34. AD5328 Input Shift Register Contents
LDAC Low (00): This option sets LDAC permanently low,
allowing the DAC registers to be updated continuously.
VDD
These bits are set when VDD is to be used as a reference. The
first group of DACs (A, B, C, and D) can be set up to use VDD by
setting Bit 0, and the second group of DACs (E, F, G, and H) by
setting Bit 1. The VDD bits have priority over the BUF bits.
LDAC High (01): This option sets LDAC permanently high.
The DAC registers are latched and the input registers can
change without affecting the contents of the DAC registers.
This is the default option for this mode.
When VDD is used as the reference, it is always unbuffered and
has an output range of 0 V to VREF regardless of the state of the
GAIN and BUF bits.
LDAC Single Update (10): This option causes a single pulse on
LDAC, updating the DAC registers once.
Reserved (11): reserved.
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