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| 型號： | AD53020 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Four Channel ECL Delay Line(四通道ECL延遲線) |
| 中文描述： | ACTIVE DELAY LINE, COMPLEMENTARY OUTPUT, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 88K |
| 代理商： | AD53020 |
–2–
REV. 0
AD53020–SPECIFICATIONS
Conditions wth all OUT and
OUT
outputs termnated through 50
V
to –2.0 V, REXT1 = 1.3 k
V
, REXT2 = 2.94 k
V
. Typical values are based on
nomnal temperature, T
A
= +25
8
C, and nomnal supply voltage, V
EE
= –5.2 V.
DC CHARACTERISTICS
1
Parameter
Symbol
T (
8
C)
Min
T yp
Max
Units
DIGIT AL INPUT HIGH VOLT AGE
IN,
IN
, DRVMODE, S0, S1
V
IH
70
–1.070
0.000
V
DIGIT AL INPUT LOW VOLT AGE
IN,
IN
, DRVMODE, S0
V
IL
V
IL
70
–1.950
–1.450
V
DIGIT AL INPUT LOW VOLT AGE, S1
70
V
EE
–1.450
V
S1 T HIRD ST AT E (EX T ENDED DELAY)
Full
V
EE
–3.2
V
DIGIT AL OUT PUT HIGH VOLT AGE
V
OH
V
OL
70
–1.000
–0.735
V
DIGIT AL OUT PUT LOW VOLT AGE
70
–1.950
–1.600
V
DIGIT AL INPUT BIAS CURRENT
IN,
IN
, DRVMODE, S0, S1
POWER SUPPLY REJECT ION RAT IO
2
–100 to
+100
I
IN
μ
A
PSRR
Full
0.5
% T pd/V
V
EE
SUPPLY CURRENT
Mode 0
Modes 1, 2
Modes 3, 5
I
EE
I
EE
I
EE
Full
Full
Full
174
225
267
200
250
290
mA
mA
mA
NOT ES
1
T he specified limits shown can be met only after thermal equilibrium has been established. T hermal equilibrium is established by applying power for at least two
minutes while maintaining a transverse air flow of 400 linear feet per minute over the device either mounted in the test socket or on the printed circuit board.
2
T his parameter is fully characterized, but not production tested.
Specifications subject to change without notice.
AD53020-Test Conditions (Unless otherwse noted): Recommended Operating
AC CHARACTERISTICS
1
Parameter
Symbol
Min
T yp
Max
Units
MINIMUM PROPAGAT ION DELAYS
2
Mode
S1
S0
0
0
0
1
0
1
2
1
0
3
1
1
5
V
EE
1
VDELAY
–0.1 V
–0.1 V
–0.1 V
–0.1 V
–0.1 V
T pd Min
T pd Min
T pd Min
T pd Min
T pd Min
3.6
4.9
3.9
5.2
6.8
4.5
6.3
5.3
7.1
8.8
5.4
7.3
6.8
8.8
10.3
ns
ns
ns
ns
ns
DELAY ADJUST MENT RANGES
Mode
S1
0
0
1
0
2
1
3
1
5
V
EE
MINIMUM PULSEWIDT H
3
S0
0
1
0
1
1
T pd Span
T pd Span
T pd Span
T pd Span
T pd Span
14.0
22.9
13.2
22.0
29.3
19.0
31.4
18.9
31.5
44.5
24.7
37.8
24.6
40.6
52.0
ns
ns
ns
ns
ns
1.9
ns
RISING EDGE DELAY VS. VWIDT H DELAY
Change (Modes 2 and 3)
3
DELAY VS. DUT Y CYCLE
3, 4
30
ps
50
ps
VWIDT H RANGE OF ADJUST MENT
(VDELAY = –0.6 V, MODES 2 AND 3, DELAY
RELAT IVE T O VWIDT H = –0.7 V)
VWIDT H = –0.1 V
VWIDT H = –1.1 V
VWIDT H = –1.3 V
–5.5
+5.5
+6.5
–4.0
ns
ns
ns
+4.0
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