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參數(shù)資料
| 型號： | AD5300BRM |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 8-Bit DAC in an SOT-23 |
| 中文描述： | SERIAL INPUT LOADING, 4 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | AD5300BRM |
AD5300
–8–
REV. A
GENERAL DESCRIPTION
D/A Section
The AD5300 DAC is fabricated on a CMOS process. The archi-
tecture consists of a string DAC followed by an output buffer
amplifier. Since there is no reference input pin, the power
supply (V
DD
) acts as the reference. Figure 20 shows a block
diagram of the DAC architecture.
V
DD
V
OUT
GND
RESISTOR
STRING
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
Figure 20. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
V
OUT
=
V
DD
×
D
256
where
D
= decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 255.
Resistor String
The resistor string section is shown in Figure 21. It is simply a
string of resistors, each of value R. The code loaded to the DAC
R
R
TO OUTPUT
AMPLIFIER
R
R
R
Figure 21. Resistor String
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
V
DD
. It is capable of driving a load of 2 k
in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figures 8 and 9. The slew rate is 1V/
μ
s
with a half-scale settling time of 4
μ
s with the output loaded.
SERIAL INTERFACE
The AD5300 has a three-wire serial interface (
SYNC
, SCLK
and DIN), which is compatible with SPI, QSPI and MICROWIRE
interface standards as well as most DSPs. See Figure 1 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the
SYNC
line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5300 compatible with high-speed
DSPs. On the sixteenth falling clock edge, the last data bit is
clocked in and the programmed function is executed (i.e., a
change in DAC register contents and/or a change in the mode of
operation). At this stage, the
SYNC
line may be kept low or be
brought high. In either case, it must be brought high for a mini-
mum of 33 ns before the next write sequence so that a falling
edge of
SYNC
can initiate the next write sequence. Since the
SYNC
buffer draws more current when V
IN
= 2.4 V than it does
when V
IN
= 0.8 V,
SYNC
should be idled low between write
sequences for even lower power operation of the part. As is
mentioned above, however, it must be brought high again just
before the next write sequence.
Input Shift Register
The input shift register is 16 bits wide (see Figure 22). The first
two bits are “don’t cares.” The next two are control bits that
control which mode of operation the part is in (normal mode or
any one of three power-down modes). There is a more complete
description of the various modes in the Power-Down Modes
section. The next eight bits are the data bits. These are trans-
ferred to the DAC register on the sixteenth falling edge of SCLK.
Finally, the last four bits are “don’t cares.”
DB0 (LSB)
DB15 (MSB)
0
0
1
1
0
1
0
1
NORMAL OPERATION
1k
V
TO GND
100k
V
TO GND
THREE-STATE
POWER-DOWN MODES
DATA BITS
X
X
PD1
PD0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Figure 22. Input Register Contents
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