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參數(shù)資料
| 型號(hào)： | AD5282BRUZ20-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 20K 256POS 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 20k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 30 ppm/°C |
| 存儲(chǔ)器類(lèi)型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 4.5 V ~ 16.5 V，±4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
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AD5280/AD5282
Rev. C | Page 17 of
28
READBACK RDAC VALUE
The AD5280/AD5282 allow the user to read back the RDAC
values in read mode. However, for the dual-channel AD5282,
the channel of interest is the one that is previously selected in
the write mode. When users need to read the RDAC values of
both channels in the AD5282, they can program the first
subaddress in write mode and then change to read mode to read
the first channel value. After that, they can change back to write
mode with the second subaddress and read the second channel
value in read mode again. It is not necessary for users to issue
the Frame 3 data byte in write mode for subsequent readback
programming format.
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5280/AD5282 feature additional programmable logic
outputs, O1 and O2, which can be used to drive a digital load,
analog switches, and logic gates. O1 and O2 default to Logic 0. The
logic states of O1 and O2 can be programmed in Frame 2 under
write mode (see Figure 45). These logic outputs have adequate
current driving capability to sink/source milliamperes of load.
Users can also activate O1 and O2 in three ways without
affecting the wiper settings by programming as follows:
Perform start, slave address, acknowledge, and instruction
bytes with O1 and O2 specified, acknowledge, stop.
Complete the write cycle with stop, then start, slave address
byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, stop.
Not complete the write cycle by not issuing the stop, then
start, slave address byte, acknowledge, instruction byte
with O1 and O2 specified, acknowledge, stop.
SELF-CONTAINED SHUTDOWN FUNCTION AND
PROGRAMMABLE PRESET
Shutdown can be activated by strobing the SHDN pin or
programming the SD bit in the write mode instruction byte.
As shown in
, when shutdown is asserted, the
AD5280/AD5282 open SWA to let the A terminal float and
short the W terminal to the B terminal. The AD5280/AD5282
consume negligible power during shutdown mode, resuming
the previous setting once the
SHDN pin is released.
In addition, shutdown can be implemented with the device
digital output as shown in Figure 47. In this configuration, the
device is shut down during power-up, but the user is allowed to
program the device at any preset levels. When it is done, the
user programs O1 high with the valid coding and the device
exits from shutdown and responds to the new setting. This self-
contained shutdown function allows absolute shutdown during
power-up, which is crucial in hazardous environments, without
adding extra components. Also, the sleep mode programming
feature during shutdown allows the AD5280/AD5282 to have a
programmable preset at any level, a solution that can be as
effective as using other high cost EEPROM devices. Because of
the extra power drawn on RPD, note that a high value should be
chosen for the RPD.
SDA
SHDN
SCL
RPD
O1
02
92
9-
0
46
Figure 47. Shutdown by Internal Logic Output
MULTIPLE DEVICES ON ONE BUS
Figure 48 shows four AD5282 devices on the same serial bus.
Each has a different slave address because the states of their Pin
AD0 and Pin AD1 are different. This allows each RDAC within
each device to be written to or read from independently. The
master device output bus line drivers are open-drain pull-
downs in a fully I2C-compatible interface.
SDA
SCL
RP
5V
MASTER
5V
SDA
AD1
AD0
AD5282
SCL
SDA
AD1
AD0
AD5282
SCL
SDA
AD1
AD0
AD5282
SCL
SDA
AD1
AD0
AD5282
SCL
02929-
047
Figure 48. Multiple AD5282 Devices on One Bus
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