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參數(shù)資料
| 型號(hào)： | AD526 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Software Programmable Gain Amplifier(軟件可編程增益放大器) |
| 中文描述： | 軟件可編程增益放大器（軟件可編程增益放大器） |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 397K |
| 代理商： | AD526 |
AD526
REV. C
–9–
T able II. Logic T able for Figure 38
V
OUT
/V
IN
A2
A1
A0
1
2
4
8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16
32
64
128
OFFSE T NULLING
Input voltage offset nulling of the AD526 is best accomplished
at a gain of 16, since the referred-to-input (RT I) offset is ampli-
fied the most at this gain and therefore is most easily trimmed.
T he resulting trimmed value of RT I voltage offset typically var-
ies less than 3
μ
V across all gain ranges.
Note that the low input current of the AD526 minimizes RT I
voltage offsets due to source resistance.
Figure 39. Offset Voltage Null Circuit
Figure 38. Cascaded Operation
OUT PUT CURRE NT BOOST E R
T he AD526 is rated for a full
±
10 V output voltage swing into
2 k
. In some applications, the need exists to drive more cur-
rent into heavier loads. As shown in Figure 40, a high current
booster may be connected “inside the loop” of the SPGA to
provide the required current boost without significantly degrad-
ing overall performance. Nonlinearities, offset and gain inaccu-
racies of the buffer are minimized by the loop gain of the
AD526 output amplifier.
Figure 40. Current Output Boosting
CASCADE D OPE RAT ION
A cascade of two AD526s can be used to achieve binarily
weighted gains from 1 to 256. If gains from 1 to 128 are needed,
no additional components are required. T his is accomplished by
using the B pin as shown in Figure 38. When the B pin is low,
the AD526 is held in a unity gain stage independent of the other
gain code values.
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