參數(shù)資料
型號(hào)： AD5248BRM100-RL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： Dual 256-Position I2C Compatible Digital Potentiometer
中文描述： DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO10
封裝： 3 X 4.90 MM, MO-187BA, MSOP-10
文件頁(yè)數(shù)： 16/20頁(yè)
文件大小： 798K
代理商： AD5248BRM100-RL7
AD5243/AD5248
I
2
C INTERFACE
I
2
C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I
2
C serial bus protocol operates as follows:
Rev. 0 | Page 16 of 20
1.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 46). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from or written to the slave
device). The AD5243 has a fixed slave address byte, while
the AD5248 has two configurable address bits AD0 and
AD1 (see Table 9).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. On the other hand, if the R/W bit is
low, the master writes to the slave device.
2.
In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A Logic Low selects Channel 1 and a
Logic High selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the previ-
ous setting is applied to the RDAC. Also, during shutdown,
new settings can be programmed. When the part is
returned from shutdown, the corresponding VR setting is
applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
care bits (see Table 9).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 46
and Figure 47).
3.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, eight data
bits are followed by an acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 48 and Figure 49).
Note that the channel of interest is the one that is previ-
ously selected in the write mode. In the case where users
need to read the RDAC values of both channels, they need
to program the first channel in the write mode and then
change to the read mode to read the first channel value.
After that, they need to change back to the write mode with
the second channel selected and read the second channel
value in the read mode again. It is not necessary for users
to issue the Frame 3 data byte in the write mode for subse-
quent readback operation. Users should refer to Figure 48
and Figure 49 for the programming format.
4.
After all data bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 46 and Figure 47). In read mode, the
master issues a no acknowledge for the ninth clock pulse
(that is, the SDA line remains high). The master then
brings the SDA line low before the tenth clock pulse, which
goes high to establish a STOP condition (see Figure 48 and
Figure 49).
A repeated write function gives the user flexibility to
update the RDAC output a number of times after
addressing and instructing the part only once. For example,
after the RDAC has acknowledged its slave address and
instruction bytes in the write mode, the RDAC output
updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a
new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
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