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| 型號(hào)： | AD5243EVAL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5243 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 數(shù)字電位器 |
| 已用 IC / 零件： | AD5243 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD5243BRMZ2.5-RL7-ND - IC POT DGTL DUAL 2.5K I2C 10MSOP AD5243BRMZ2.5-ND - IC POT DGTL DUAL 2.5K I2C 10MSOP AD5243BRMZ50-ND - IC POT DGTL DUAL 256POS 10-MSOP AD5243BRMZ10-RL7-ND - IC DGTL POT DUAL 10K 10-MSOP AD5243BRMZ100-RL7-ND - IC DGTL POT DUAL 100K 10-MSOP AD5243BRMZ50-RL7-ND - IC DGTL POT DUAL 50K 10-MSOP AD5243BRMZ100-ND - IC DGTL POT DUAL 100K I2C 10MSOP AD5243BRMZ10-ND - IC DGTL POT DUAL 10K I2C 10-MSOP AD5243BRM50-RL7-ND - IC DGTL POT DUAL 50K I2C 10-MSOP AD5243BRM50-ND - IC DGTL POT DUAL 50K I2C 10-MSOP 更多... |
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AD5243/AD5248
Data Sheet
Rev. B | Page 16 of 20
I2C INTERFACE
I2C COMPATIBLE, 2-WIRE SERIAL BUS
The 2-wire, I2C-compatible serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from or written to the slave
device). The AD5243 has a fixed slave address byte,
whereas the AD5248 has two configurable address bits,
AD0 and AD1 (see Figure 10).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is called the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master reads
from the slave device. On the other hand, if the R/W bit is
low, the master writes to the slave device.
2. In the write mode, the second byte is the instruction byte.
The first bit (MSB) of the instruction byte is the RDAC
subaddress select bit. A logic low selects Channel 1 and a
logic high selects Channel 2.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When the AD5243 or AD5248 is
brought out of shutdown, the previous setting is applied to
the RDAC. In addition, during shutdown, new settings can
be programmed. When the part is returned from shutdown,
the corresponding VR setting is applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
care bits (see Figure 10).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 45
and Figure 46).
3. In the read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference with the write mode, where there are eight data bits
followed by an acknowledge bit). Similarly, the transitions
on the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Figure 47
and Figure 48).
Note that the channel of interest is the one that is previously
selected in write mode. If users need to read the RDAC
values of both channels, they need to program the first
channel in write mode and then change to read mode to
read the first channel value. After that, the user must return
the device to write mode with the second channel selected
and read the second channel value in read mode. It is not
necessary for users to issue the Frame 3 data byte in write
mode for subsequent readback operation. Users should refer
to Figure 47 and Figure 48 for the programming format.
4. After all data bits have been read or written, a stop condition
is established by the master. A stop condition is defined as
a low-to-high transition on the SDA line while SCL is high.
In write mode, the master pulls the SDA line high during
45 and Figure 46). In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, which goes high to establish a
stop condition (see Figure 47 and Figure 48).
A repeated write function provides the user with the flexibility
of updating the RDAC output multiple times after addressing
and instructing the part only once. For example, after the
RDAC has acknowledged its slave address and instruction
bytes in write mode, the RDAC output updates on each
successive byte. If different instructions are needed, however,
the write/read mode must restart with a new slave address,
instruction, and data byte. Similarly, a repeated read function
of the RDAC is also allowed.
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