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參數(shù)資料
| 型號： | AD5243EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Dual 256-Position I2C Compatible Digital Potentiometer |
| 中文描述： | 雙256位I2C兼容數(shù)字電位器 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 798K |
| 代理商： | AD5243EVAL |
AD5243/AD5248
Table 9. Write Mode
AD5243
S
0
1
AD5248
S
0
1
Rev. 0 | Page 17 of 20
0
Slave Address Byte
1
1
1
1
W
A
A0
SD
X
Instruction Byte
X
X
X
X
X
A
D7
D6
D5
D4
Data Byte
D3
D2
D1
A
P
0
1
1
AD1
AD0
W
A
A0
SD
X
X
X
X
X
X
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Instruction Byte
Data Byte
Table 10. Read Mode
AD5243
S
0
AD5248
S
0
1
1
0
1
1
1
1
R
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Slave Address Byte
Data Byte
0
1
Slave Address Byte
1
AD1
AD0
R
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
Data Byte
LEGEND
S = Start condition.
P = Stop condition.
A = Acknowledge.
X = Don’t care.
W = Write.
AD0, AD1 = Package pin
programmable address bits.
R = Read.
A0 = RDAC subaddress select bit.
SD = Shutdown connects wiper to B terminal and
open circuits A terminal. It does not change contents
of wiper register.
D7, D6, D5, D4, D3, D2, D1, D0 = Data bits.
0
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
P
S
S
SCL
SDA
P
Figure 45. I
2
C Interface Detailed Timing Diagram
0
SCL
START BY
MASTER
SDA
0
1
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
1
1
1
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5243
R/W
A0
SD
X
X
X
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5243
FRAME 3
DATA BYTE
1
9
X
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5243
X
Figure 46. Writing to the RDAC Register—AD5243
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