參數(shù)資料
型號: AD5235BRUZ250
廠商: Analog Devices Inc
文件頁數(shù): 17/32頁
文件大?。?/td> 0K
描述: IC DGTL POT DUAL 1024POS 16TSSOP
產(chǎn)品變化通告: Metal Edit Change 03/Feb/2012
標準包裝: 96
接片: 1024
電阻(歐姆): 250k
電路數(shù): 2
溫度系數(shù): 標準值 35 ppm/°C
存儲器類型: 非易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 3 V ~ 5.5 V,±2.25 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
AD5235
Data Sheet
Rev. F | Page 24 of 32
APPLICATIONS INFORMATION
BIPOLAR OPERATION FROM DUAL SUPPLIES
The AD5235 can be operated from ±2.5 V dual supplies, which
enable control of ground referenced ac signals or bipolar operation.
AC signals as high as VDD and VSS can be applied directly across
Terminal A to Terminal B with the output taken from Terminal W.
See Figure 47 for a typical circuit connection.
±2.5V p-p
AD5235
VSS
GND
SDI
CLK
SS
SCLK
MOSI
GND
VDD
MICRO-
CONTROLLER
±1.25V p-p
VDD
+2.5V
–2.5V
CS
D = MIDSCALE
A
W
B
02816-
046
Figure 47. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION
A digital potentiometer is commonly used in gain control such
as the noninverting gain amplifier shown in Figure 48.
U1
VO
R2
02816-
047
250k
VI
R1
47k
C1
11pF
W
B
A
C2
2.2pF
Figure 48. Typical Noninverting Gain Amplifier
When the RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node, it introduces a zero for the 1/βO
term with 20 dB/dec, whereas a typical op amp gain bandwidth
product (GBP) has 20 dB/dec characteristics. A large R2 and
finite C1 can cause the frequency of this zero to fall well below
the crossover frequency. Therefore, the rate of closure becomes
40 dB/dec, and the system has a 0° phase margin at the crossover
frequency. If an input is a rectangular pulse or step function, the
output can ring or oscillate. Similarly, it is also likely to ring when
switching between two gain values; this is equivalent to a stop
change at the input.
Depending on the op amp GBP, reducing the feedback resistor
might extend the frequency of the zero far enough to overcome
the problem. A better approach is to include a compensation
capacitor, C2, to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2. This is not
an option because of the variation of R2. As a result, one can
use the previous relationship and scale C2 as if R2 were at its
maximum value. Doing this might overcompensate and
compromise the performance when R2 is set at low values.
Alternatively, it avoids the ringing or oscillation at the worst
case. For critical applications, find C2 empirically to suit the
oscillation. In general, C2 in the range of a few picofarads to
no more than a few tenths of picofarads is usually adequate
for the compensation.
Similarly, W and A terminal capacitances are connected to the
output (not shown); their effect at this node is less significant
and the compensation can be avoided in most cases.
HIGH VOLTAGE OPERATION
The digital potentiometer can be placed directly in the feedback or
input path of an op amp for gain control, provided that the voltage
across Terminal A to Terminal B, Terminal W to Terminal A or
Terminal W to Terminal B does not exceed |5 V|. When high
voltage gain is needed, set a fixed gain in the op amp and let the
digital potentiometer control the adjustable input. Figure 49
shows a simple implementation.
2R
R
VO
A1
V+
V–
15V
0V TO 15V
02816-
048
C
A
B
W
AD5235
5V
Figure 49. 15 V Voltage Span Control
Similarly, a compensation capacitor, C, may be needed to dampen
the potential ringing when the digital potentiometer changes
steps. This effect is prominent when stray capacitance at the
inverted node is augmented by a large feedback resistor. Typically,
a picofarad Capacitor C is adequate to combat the problem.
DAC
For DAC operation (see Figure 50), it is common to buffer the
output of the digital potentiometer unless the load is much larger
than RWB. The buffer serves the purpose of impedance
conversion and can drive heavier loads.
AD8601
V+
V–
5V
VO
A1
02816-
049
AD1582
GND
VIN
VOUT
3
2
5V
U1
1
AD5235
A
B
W
Figure 50. Unipolar 10-Bit DAC
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