V
參數(shù)資料
型號(hào)： AD5231BRUZ10
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/28頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL 1024POS 16-TSSOP
標(biāo)準(zhǔn)包裝： 96
接片： 1024
電阻（歐姆）： 10k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 600 ppm/°C
存儲(chǔ)器類型： 非易失
接口： 4 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V，±2.25 V ~ 2.75 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 787 (CN2011-ZH PDF)
AD5231
Data Sheet
Rev. D | Page 4 of 28
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
POWER SUPPLIES
Single-Supply Power Range
VDD
VSS = 0 V
2.7
5.5
V
Dual-Supply Power Range
VDD/VSS
±2.25
±2.75
V
Positive Supply Current
IDD
VIH = VDD or VIL = GND
2.7
10
A
Negative Supply Current
ISS
VIH = VDD or VIL = GND,
VDD = +2.5 V, VSS = 2.5 V
0.5
10
A
EEMEM Store Mode Current
IDD (store)
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
40
mA
ISS (store)
VDD = +2.5 V, VSS = 2.5 V
40
mA
EEMEM Restore Mode Current7
IDD (restore)
VIH = VDD or VIL = GND,
VSS = GND, ISS ≈ 0
0.3
3
9
mA
ISS (restore)
VDD = +2.5 V, VSS = 2.5 V
0.3
3
9
mA
Power Dissipation8
PDISS
VIH = VDD or VIL = GND
0.018
0.05
mW
Power Supply Sensitivity5
PSS
ΔVDD = 5 V ± 10%
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS5, 9
Bandwidth
BW
3 dB, RAB = 10 k/50 k/
100 k
370/85/44
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 k
0.045
%
VA = 1 V rms, VB = 0 V, f = 1 kHz,
RAB = 50 k, 100 k
0.022
%
VW Settling Time
tS
VA = VDD, VB = 0 V,
VW = 0.50% error band,
Code 0x000 to 0x200
for RAB = 10 k/50 k/100 k
1.2/3.7/7
s
Resistor Noise Voltage
eN_WB
RWB = 5 k, f = 1 kHz
9
nV/√Hz
1
Typical values represent average readings at 25°C and VDD = 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 A @ VDD = 2.7 V and IW ~ 400 A @ VDD = 5 V for the
RAB = 10 k version, IW ~ 50 A for the RAB = 50 k, and IW ~ 25 A for the RAB = 100 k version (see Figure 26).
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of
1 LSB minimum are guaranteed monotonic operating condition (see Figure 27).
4
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-
referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.
7
EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 23). To minimize
power dissipation, a NOP Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).
8
PDISS is calculated from (IDD × VDD) + (ISS × VSS).
9
All dynamic characteristics use VDD = +2.5 V and VSS = 2.5 V.
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AD5231BRUZ10 制造商:Analog Devices 功能描述:Digital Potentiometer (Pots) IC
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