VDD = 5 V ± 10%, or 3 V ± 10" />
參數(shù)資料
型號(hào)： AD5160BRJZ100-R2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 0K
描述： IC DGTL POT 100K SPI SOT23-8
標(biāo)準(zhǔn)包裝： 1
接片： 256
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 45 ppm/°C
存儲(chǔ)器類(lèi)型： 易失
接口： 3 線(xiàn)串行（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-8
供應(yīng)商設(shè)備封裝： SOT-23-8
包裝： 剪切帶 (CT)
其它名稱(chēng)： AD5160BRJZ100R2CT
AD5160
Rev. B | Page 4 of 16
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; 40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity2
R-DNL
RWB, VA = no connect
1
±0.1
+1
LSB
Resistor Integral Nonlinearity2
R-INL
RWB, VA = no connect
2
±0.25
+2
LSB
Nominal Resistor Tolerance3
RAB
TA = 25°C
15
+15
%
Resistance Temperature Coefficient
RAB/T
VAB = VDD,
Wiper = no connect
45
ppm/°C
Wiper Resistance
RW
VDD = 5 V
50
120
Ω
Potentiometer Divider Mode
Specifications apply to all VRs
Resolution
N
8
Bits
Differential Nonlinearity4
DNL
1
±0.1
+1
LSB
Integral Nonlinearity4
INL
1
±0.3
+1
LSB
Voltage Divider Temperature
Coefficient
VW/T
Code = 0x80
15
ppm/°C
Full-Scale Error
VWFSE
Code = 0xFF
3
1
0
LSB
Zero-Scale Error
VWZSE
Code = 0x00
0
1
3
LSB
RESISTOR TERMINALS
Voltage Range5
VA,B,W
GND
VDD
V
Capacitance A, Capacitance B6
CA,B
f = 1 MHz, measured to GND, code =
0x80
45
pF
Capacitance W6
CW
f = 1 MHz, measured to GND, code =
0x80
60
pF
Common-Mode Leakage
ICM
VA = VB = VDD/2
1
nA
DIGITAL INPUTS
Input Logic High
VIH
2.4
V
Input Logic Low
VIL
0.8
V
Input Logic High
VIH
VDD = 3 V
2.1
V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current
IIL
VIN = 0 V or 5 V
±1
μA
Input Capacitance6
CIL
5
pF
POWER SUPPLIES
Power Supply Range
VDD RANGE
2.7
5.5
V
Supply Current
IDD
VIH = 5 V or VIL = 0 V
3
8
μA
Power Dissipation7
PDISS
VIH = 5 V or VIL = 0 V, VDD = 5 V
0.2
mW
Power Supply Sensitivity
PSS
VDD = +5 V ± 10%, code = midscale
±0.02
±0.05
%/%
DYNAMIC CHARACTERISTICS6, 8
Bandwidth –3 dB
BW
RAB = 10 kΩ/50 kΩ/100 kΩ, Code = 0x80
600/100/40
kHz
Total Harmonic Distortion
THDW
VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB =
10 kΩ
0.05
%
VW Settling Time (10 kΩ/50 kΩ/100 kΩ)
tS
VA = 5 V, VB = 0 V,
±1 LSB error band
2
μs
Resistor Noise Voltage Density
eN_WB
RWB = 5 kΩ
9
nV/√Hz
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). VA = VDD and VB =
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
8 All dynamic characteristics use VDD = 5 V.
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