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參數(shù)資料
| 型號(hào)： | AD5063BRMZ-REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT 2.7-5.5V 10MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 333k |
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AD5063
Rev. C | Page 13 of
20
THEORY OF OPERATION
The AD5063 is a single 16-bit, serial input, voltage-output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is
written to the AD5063 in a 24-bit word format via a 3-wire serial
interface.
The AD5063 incorporates a power-on reset circuit that ensures
the DAC output powers up to midscale. The device also has a
software power-down mode pin that reduces the typical current
consumption to less than 1 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5063 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 27. The four MSBs of the 16-bit data-word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either the DACGND or VREF
buffer output. The remaining 12 bits of the data-word drive
Switches S0 to S11 of a 12-bit voltage mode R-2R ladder
network.
2R
0
4
76
6-
02
7
S0
VREF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
VOUT
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 27. DAC Ladder Structure
REFERENCE BUFFER
The AD5063 operates with an external reference. The reference
input (VREF) has an input range of 2 V to AVDD 50 mV. This
input voltage is used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5063 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. (See
for a
timing diagram of a typical write sequence.)
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the SYNC line can be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence, so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when VIH = 1.8 V than it does when
VIH = 0.8 V, SYNC should be idled low between write sequences
for even lower power operation of the part. As previously indi-
cated, however, it must be brought high again just before the
next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 28). PD1
and PD0 are bits that control the operating mode of the part
(normal mode or any one of the three power-down modes).
There is a more complete description of the various modes in
the Power-Down Modes section. The next 16 bits are the data
bits. These are transferred to the DAC register on the 24th falling
edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, it acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see
).
DATA BITS
DB15 (MSB)
DB0 (LSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
1k TO GND
100k TO GND
THREE-STATE
POWER-DOWN MODES
0
1
0
1
0
1
04
766-
028
00
0
PD1
PD0
Figure 28. Input Register Contents
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5063BRMZ-REEL71 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V in an MSOP |
| AD5064 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Industrial Current/Voltage Output Driver |
| AD50641 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Fully Accurate, 16-Bit, Unbuffered VOUT, Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP |
| AD50643-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD50647-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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