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參數(shù)資料
| 型號(hào)： | AD420ARZ-32 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC SRL 16BIT 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 設(shè)置時(shí)間： | 2.5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 176mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 2 電流，雙極 |
| 采樣率（每秒）： | 400 |
| 產(chǎn)品目錄頁(yè)面： | 781 (CN2011-ZH PDF) |
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AD420
Rev. H | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00
49
4-
00
2
NC 1
VLL 2
FAULT DETECT 3
RANGE SELECT 2 4
NC
24
VCC
23
NC
22
CAP 2
21
RANGE SELECT 1 5
CAP 1
20
CLEAR 6
BOOST
19
LATCH 7
IOUT
18
CLOCK 8
VOUT
17
DATA IN 9
OFFSET TRIM
16
DATA OUT 10
REF IN
15
GND 11
REF OUT
14
NC 12
NC
13
NC = NO CONNECT
AD420
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Function
1, 12,
13, 24
NC
No Connection. No internal connections inside device.
2
VLL
Auxiliary buffered +4.5 V digital logic voltage. This pin is the internal supply voltage for the digital
circuitry and can be used as a termination for pull-up resistors. An external +5 V power supply can be
connected to VLL. It will override this buffered voltage, thus reducing the internal power dissipation. The
section.
3
FAULT DETECT
FAULT DETECT, connected to a pull-up resistor, is asserted low when the output current does not match
the DAC’s programmed value, for example, in case the current loop is broken.
4
RANGE SELECT 2
Selects the converter’s output operating range. One output voltage range and three
5
RANGE SELECT 1
output current ranges are available.
6
CLEAR
Valid VIH unconditionally forces the output to go to the minimum of its programmed range. After CLEAR
is removed the DAC output will remain at this value. The data in the input register is unaffected.
7
LATCH
In the 3-wire interface mode a rising edge parallel loads the serial input register data into the DAC. To
use the asynchronous mode connect LATCH through a current limiting resistor to VCC.
8
CLOCK
Data Clock Input. The clock period is equal to the input data bit rate in the 3-wire interface mode and is
16 times the bit rate in asynchronous mode.
9
DATA IN
Serial Data Input.
10
DATA OUT
Serial Data Output. In the 3-wire interface mode, this output can be used for daisy-chaining multiple
AD420s. In the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is
received.
11
GND
Ground (Common).
14
REF OUT
+5 V Reference Output.
15
REF IN
Reference Input.
16
OFFSET TRIM
Offset Adjust.
17
VOUT
Voltage Output.
18
IOUT
Current Output.
19
BOOST
Connect to an external transistor to reduce the power dissipated in the AD420 output transistor, if
desired.
20
CAP 1
These pins are used for internal filtering. Connect capacitors between each of these
21
CAP 2
pins and VCC. Refer to the description of current output operation.
22
NC
No Connection. Do not connect anything to this pin.
23
VCC
Power Supply Input. The VCC pin should always be decoupled to GND with a 0.1 μF capacitor. See the
Power Supplies and Decoupling section.
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