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參數(shù)資料
| 型號(hào)： | AD1854JRSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO 96KHZ 5V 28SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Interfacing AV Converters to Blackfin Processors Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | DSP，I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 250mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 產(chǎn)品目錄頁(yè)面： | 781 (CN2011-ZH PDF) |
AD1854
–5–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin
Input/Output
Pin Name
Description
1
I
DGND
Digital Ground.
2
I
MCLK
Master Clock Input. Connect to an external clock source at either 256, 384
or 512 FS.
3
I
CLATCH
Latch input for control data. This input is rising-edge sensitive.
4
I
CCLK
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
5
I
CDATA
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel-specific attenuation and mute.
6
I
384/256
Selects the master clock mode as either 384 times the intended sample
frequency (HI) or 256 times the intended sample frequency (LO). The state
of this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1854 is in power-down/reset. It must not be changed while the
AD1854 is operational.
7
I
X2MCLK
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
8
O
ZEROR
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
9
I
DEEMP
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50
s/15 s response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
10
I
96/48
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
11, 15
I
AGND
Analog Ground.
12
O
OUTR+
Right Channel Positive line level analog output.
13
O
OUTR–
Right Channel Negative line level analog output.
14
O
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10
F and 0.1 F capacitors to the AGND.
16
O
OUTL–
Left Channel Negative line level analog output.
17
O
OUTL+
Left Channel Positive line level analog output.
18
I
AVDD
Analog Power Supply. Connect to analog 5 V supply.
19
O
FILTB
Filter Capacitor connection, connect 10
F capacitor to AGND.
20
I
IDPM1
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
21
I
IDPM0
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
22
O
ZEROL
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
23
I
MUTE
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
24
I
PD/RST
Power-Down/Reset. The AD1854 is placed in a low power consumption
mode when this pin is held LO. The AD1854 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
25
I
L/RCLK
Left/Right clock input for input data. Must run continuously.
26
I
BCLK
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
27
I
SDATA
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
28
I
DVDD
Digital Power Supply Connect to digital 5 V supply.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1854JRSZRL | 功能描述:IC DAC STEREO 96KHZ 5V 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD1854KRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1854KRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH DELTA-SIGMA 24BIT 28SSOP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Tape and Reel |
| AD1855 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Stereo, 96 kHz, Multibit DAC |
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