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參數(shù)資料
| 型號： | AD1671KP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC SNGL 12BIT 28PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 750mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；2 個單端，單極 |
AD1671
(TMIN to TMAX with VCC = +5 V
5%, VLOGIC = +5 V
10%, VEE = –5 V
5%, fSAMPLE = 1 MSPS,
flNPUT = 1OO kHz, unless otherwise noted)
1
AC SPECIFICATIONS
AD1671J/A/S
AD1671K
Parameter
Min
Typ
Max
Min
Typ
Max
Units
SIGNAL-TO-NOISE PLUS DISTORTION RATIO
(S/N + D)
–0.5 dB Input
68
70
68
71
dB
–20 dB Input
50
51
dB
EFFECTIVE NUMBER OF BITS (ENOB)
11.2
Bits
TOTAL HARMONIC DISTORTION (THD)
–80
–75
–83
–75
dB
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
–80
–77
–81
–77
dB
SMALL SIGNAL BANDWIDTH
12
MHz
FULL POWER BANDWIDTH
2
MHz
INTERMODULATION DISTORTION (IMD)
2
2nd Order Products
–80
–75
–80
–75
dB
3rd Order Products
–85
–75
–85
–75
dB
NOTES
1f
IN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a 0 dB ( ± 5 V) input signal, unless otherwise
indicated.
2f
A = 99 kHz, fB = 100 kHz with fSAMPLE = 1 MSPS.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Parameters
Symbol
Min
Typ
Max
Units
Conversion Time
tC
800
ns
Sample Rate
FS
1.25
MSPS
ENCODE Pulse Width High (Figure 1a)
tENC
20
50
ns
ENCODE Pulse Width Low (Figure 1b)
tENCL
20
ns
DAV Pulse Width
tDAV
150
300
ns
ENCODE Falling Edge Delay
tF
0ns
Start New Conversion Delay
tR
0ns
Data and OTR Delay from DAV Falling Edge
tDD
1
20
75
ns
Data and OTR Valid before DAV Rising Edge
tSS
2
20
75
ns
NOTES
1t
DD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2t
SS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
Specifications subject to change without notice.
(For all grades TMIN to TMAX with VCC = +5 V
5%, VLO61C = +5 V
10%,
VEE = –5 V
5%; VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
ENCODE
DAV
DATA 0 (PREVIOUS)
DATA 1
C
t
DAV
t
DD
t
SS
t
F
t
R
t
ENCL
BIT 1–12
MSB, OTR
Figure 1b. Encode Pulse LOW
ENCODE
DAV
DATA 0 (PREVIOUS)
DATA 1
ENC
t
C
t
DAV
t
DD
t
SS
t
R
t
BIT 1–12
MSB, OTR
Figure 1a. Encode Pulse HIGH
REV. B
–3–
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