參數(shù)資料
型號(hào): ACH16821DGG
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 通用總線(xiàn)功能
英文描述: 20-bit bus-interface D-type flip-flop; positive-edge trigger 3-State
中文描述: ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: PLASTIC, TSSOP2-56
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 95K
代理商: ACH16821DGG
Philips Semiconductors
Product specification
74ALVCH16821
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
1998 May 29
7
AC CHARACTERISTICS FOR V
CC
= 2.3V TO 2.7V RANGE
GND = 0V; t
r
= t
f
2.0ns; C
L
= 30pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 2.5V
±
0.2V
TYP
1
UNIT
MIN
MAX
t
PLH
/t
PHL
Propagation delay
nCP to nQ
n
3-State output enable time
nOE
n
to nQ
n
3-State output disable time
nOE
n
to nQ
n
nCP pulse width HIGH or LOW
Set up time nD
n
to nCP
Hold time nD
n
to nCP
Maximum clock pulse frequency
1, 4
1.0
2.6
5.8
ns
t
PZH
/t
PZL
2, 4
1.0
2.8
6.6
ns
t
PHZ
/t
PLZ
2, 4
1.0
2.2
5.7
ns
t
W
t
SU
t
h
F
max
3, 4
3, 4
3, 4
1, 4
3.0
1.4
0.4
150
1.8
0.3
0.0
250
ns
ns
ns
MHz
NOTE:
1. All typical values are at V
CC
= 2.5V and T
amb
= 25
°
C.
AC CHARACTERISTICS FOR V
CC
= 3.0V TO 3.6V RANGE AND V
CC
= 2.7V
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3
±
0.3V
TYP
1
V
CC
= 2.7V
TYP
1
UNIT
MIN
MAX
MIN
MAX
t
PHL
/t
PLH
Propagation delay
nCP to nQ
n
3-State output enable time
nOE
n
to nQ
n
3-State output disable time
nOE
n
to nQ
n
nCP pulse width HIGH or
LOW
Set up time nD
n
to nCP
Hold time nD
n
to nCP
Maximum clock pulse
frequency
1, 4
1.0
2.5
4.5
1.0
2.8
5.3
ns
t
PZH
/t
PZL
2, 4
1.0
2.3
5.1
1.0
3.2
6.2
ns
t
PHZ
/t
PLZ
2, 4
1.0
2.8
4.6
1.0
3.1
5.0
ns
t
W
3, 4
3.3
0.2
3.3
1.7
ns
t
SU
t
h
3, 4
3, 4
1.0
0.8
0.2
0.4
1.2
0.6
0.3
–0.3
ns
ns
F
max
1, 4
150
350
150
300
MHz
NOTES:
1. All typical values are at T
amb
= 25
°
C.
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