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2009 Microchip Technology Inc.
DS41341E-page 35
PIC16F72X/PIC16LF72X
3.1
MCLR
The PIC16F72X/PIC16LF72X has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR pin
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to VDD. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
3.2
Power-on Reset (POR)
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum
rise
time
for
VDD
is
required.
See
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
3.3
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
VDD variation
Temperature variation
Process variation
See
DC
parameters
for
details
3.4
Watchdog Timer (WDT)
The WDT has the following features:
Shares an 8-bit prescaler with Timer0
Time-out period is from 17 ms to 2.2 seconds,
nominal
Enabled by a Configuration bit
WDT is cleared under certain conditions described in
3.4.1
WDT OSCILLATOR
The WDT derives its time base from 31 kHz internal
oscillator.
VDD
PIC MCU
MCLR
R1
10 k
Ω
C1
0.1
μF
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
Note:
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).