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參數(shù)資料
| 型號： | AAT3141 |
| 廠商： | Advanced Analogic Technologies, Inc. |
| 英文描述： | High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications |
| 中文描述： | 高效率1x/1.5x/2x電荷泵白光LED應用 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 481K |
| 代理商： | AAT3141 |
AAT3141
High Efficiency 1X/1.5X/2X Charge Pump
for White LED Applications
12
3141.2004.07.0.91
AS
2
Cwire Serial Interface
The current source output magnitude is controlled
by the Advanced Simple Serial Control (AS
2
Cwire)
serial digital input. AS
2
Cwire adds addressing
capability for multiple data registers over the
Simple Serial Control (S
2
Cwire), which is only
capable of controlling a single register. The
AAT3141 has two registers. One contains the cur-
rent level setting for outputs D1-D3, and the other
contains the current level setting for output D4.
Three addresses are used to control the two regis-
ters. Address 0 addresses both registers simulta-
neously to allow the loading of both registers with
the same data using a single write protocol.
Address 1 addresses register 1 for D1-D3 current
level settings. Address 2 addresses register 2 for
D4 current level settings.
As with S
2
Cwire, AS
2
Cwire relies on the number of
rising edges of the EN/SET pin to address and load
the registers. AS
2
Cwire latches data or address
after the EN/SET pin has been held high for time
T
LAT
. Address or data is differentiated by the num-
ber of EN/SET rising edges. Since the data regis-
ters are 5 bits each, the differentiating number of
pulses is 2
5
or 32, so that address 0 is signified by
33 rising edges, address 1 by 34 rising edges and
address 2 by 35 rising edges. Data is set to any
number of rising edges between 1 and including
32. Atypical write protocol is a burst of EN/SET ris-
ing edges, signifying a particular address, followed
by a pause with EN/SET held high for the T
LAT
time-
out period, a burst of rising edges signifying data,
and a T
LAT
timeout for the data registers. Once an
address is set, then multiple writes to the corre-
sponding data register are allowed. Address 0 is
the default address on the first rising edge after the
AAT3141 has been disabled. If data is presented
on the first rising edge with no prior address, both
data registers are simultaneously loaded.
When EN/SET is held low for an amount of time
greater than T
OFF
, the AAT3141 enters into shutdown
IN
. Data and
Address registers are reset to 0 during shutdown.
AS
2
Cwire Serial Interface Addressing
AS
2
Cwire Serial Interface Timing
Address
Data
1
EN/SET
2
33
34
Address
Data Reg 1
Data Reg 2
1
2 . . .
n <= 32
0
1
0
0
n
T
HI
T
LO
T
LAT
T
LAT
Address
EN/SET Rising Edges
Data Register
0
1
2
33
34
35
1 & 2: D1-D4
1: D1-D3
2: D4
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AAT3141_07 | 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications |
| AAT3141ITP-T1 | 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications |
| AAT3142 | 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications |
| AAT3142_07 | 制造商:ANALOGICTECH 制造商全稱:Advanced Analogic Technologies 功能描述:High Efficiency 1X/1.5X/2X Charge Pump for White LED Applications |
| AAT3142ITP-T1 | 制造商:Skyworks Solutions Inc 功能描述:LED DRIVER IC |
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