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AAT2158
1.5A Low Noise Step-Down Converter
2158.2007.10.1.1
11
Component Selection
Inductor Selection
The step-down converter uses peak current mode
control with slope compensation to maintain stability
for duty cycles greater than 50%. The output inductor
value must be selected so the inductor current down
slope meets the internal slope compensation require-
ments. The inductor should be set equal to the out-
put voltage numeric value in μH. This guarantees that
there is sufficient internal slope compensation.
Manufacturer's specifications list both the inductor
DC current rating, which is a thermal limitation, and
the peak current rating, which is determined by the
saturation characteristics. The inductor should not
show any appreciable saturation under normal load
conditions. Some inductors may meet the peak and
average current ratings yet result in excessive loss-
es due to a high DCR. Always consider the losses
associated with the DCR and its effect on the total
converter efficiency when selecting an inductor.
The 3.3μH CDRH4D28 series Sumida inductor has
a 49.2m
Ω
worst case DCR and a 1.57A DC current
rating. At full 1.5A load, the inductor DC loss is
97mW which gives less than 1.5% loss in efficien-
cy for a 1.5A, 3.3V output.
Input Capacitor
Select a 10μF to 22μF X7R or X5R ceramic capac-
itor for the input. To estimate the required input
capacitor size, determine the acceptable input rip-
ple level (V
PP
) and solve for C. The calculated
value varies with input voltage and is a maximum
when V
IN
is double the output voltage.
Always examine the ceramic capacitor DC voltage
coefficient characteristics when selecting the prop-
er value. For example, the capacitance of a 10μF,
6.3V, X5R ceramic capacitor with 5.0V DC applied
is actually about 6μF.
The maximum input capacitor RMS current is:
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current.
for V
IN
= 2 · V
O
The term
voltage ripple and input capacitor RMS current
equations and is a maximum when V
O
is twice V
IN
.
This is why the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT2158. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1)
can be seen in the evaluation board layout in the
Layout section of this datasheet (see Figure 2).
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the
evaluation board input voltage pins. The inductance
of these wires, along with the low-ESR ceramic input
capacitor, can create a high Q network that may
affect converter performance. This problem often
becomes apparent in the form of excessive ringing in
the output voltage during load transients. Errors in the
loop phase and gain measurements can also result.
appears in both the input
· 1
-
IN
V
O
V
IN
I
O
2
RMS(MAX)
I
=
· 1
-
= D
· (1 - D) = 0.5
2
=
V
IN
V
O
V
IN
O
1
2
I
RMS
= I
O
· · 1
-
V
IN
V
O
V
IN
C
IN(MIN)
=
1
- ESR
·
4
·
F
S
I
O
V
PP
· 1
-
= 1
IN
= 2
·
V
O
V
IN
V
IN
O
V
O
4
· 1
-
V
O
V
IN
C
IN
=
V
O
V
IN
- ESR
·
F
S
V
PP
I
O