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參數(shù)資料
| 型號： | A8423KL |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | LIN Bus Transceiver with Integrated Voltage Regulator |
| 中文描述： | LIN總線收發(fā)器集成穩(wěn)壓器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 368K |
| 代理商： | A8423KL |
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
D
A
A8423
LIN Bus Transceiver with Integrated Voltage Regulator
Preliminary – Subject to Change
Without Notice February 9, 2004
DYNAMIC CHARACTERISTICS
at T
J
= –40°C to 150oC, V
SUP
= 7 V to 18 V (unless otherwise noted)
Characteristics
Symbol
S
HL
Test Conditions
Min.
1
1
–
–2
–
–
–
–
–
–
–
–
Typ.
2
2
1
–
1.5
1.5
–
3
3
–
1.8
50
Max.
3
3
–
2
4
4
2
6
6
2
–
–
Units
V/μs
V/μs
V/μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
LIN Falling Edge Slew Rate
1
80% to 20%
20% to 80% into >1 k
and < 5 nF
20% to 80% into >1 k
and < 10 nF
20% to 80% into > 1 k
and < 5 nF
TX H
→
L; LIN crossing 95%
TX L
→
H; LIN crossing 5%
LIN Rising Edge Slew Rate
1
S
LH
LIN Rise Fall Symmetry
TX Propagation Delay H
→
L
TX Propagation Delay L
→
H
TX Propagation Delay Matching
RX Propagation Delay H
→
L
RX Propagation Delay L
→
H
RX Propagation Delay Matching
Glitch Rejection
Wake-up Delay (LIN or WAKE)
Thermal Shutdown
Shutdown Temperature
Thermal Shutdown Hysteresis
1
Slew rate is controlled during both transitions and will not exceed speci
fi
ed limits at any point between test limits.
t
SYM
t
TXL
t
TXH
t
RXL
t
RXH
LIN crossing 40%; RX crossing 50%
LIN crossing 60%; RX crossing 50%
t
GLR
t
WL
+ve and -ve pulse rejection on LIN (to RX)
Wake-up to INH
T
SD
T
HYS
–
–
165
20
–
–
oC
oC
40%
60%
5%
95%
50%
50%
t
TXL
t
TXH
t
RXL
t
RXH
TX
RX
LIN
Figure 1. Propagation timing de
fi
nition
80
20
LIN
S
LH
t
V
LIN
S
HL
(%)
Figure 2. Slew rate de
fi
nition
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