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參數(shù)資料
| 型號(hào)： | A6809SLW |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
| 中文描述： | 達(dá)比奇第四，10位串行輸入，鎖存源極驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | A6809SLW |
6809
AND
6810
10-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
www.allegromicro.com
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are V
DD
and Ground)
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the
respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as
long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the
BLANKING input be high during serial data entry.
When the BLANKING input is high, the output source
drivers are disabled (OFF); the pnp active pull-down sink
drivers are ON. The information stored in the latches is not
affected by the BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of their respective
latches.
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
OUT
N
Dwg. WP-029
50%
SERIAL
DATA OUT
DATA
DATA
10%
90%
50%
50%
50%
C
A
B
D
E
LOW = ALL OUTPUTS ENABLED
p(STH-QL)
t
p(CH-SQX)
t
DATA
p(STH-QH)
t
BLANKING
OUT
N
Dwg. WP-030
DATA
10%
50%
en(BQ)
t
dis(BQ)
t
HIGH = ALL OUTPUTS BLANKED (DISABLED)
90%
r
t
f
t
A.
Data Active Time Before Clock Pulse
(Data Set-Up Time), t
su(D)
.........................................
25 ns
B.
Data Active Time After Clock Pulse
(Data Hold Time), t
h(D)
...............................................
25 ns
C.
Clock Pulse Width, t
w(CH)
...............................................
50 ns
D.
Time Between Clock Activation and Strobe, t
su(C)
.......
100 ns
E.
Strobe Pulse Width, t
w(STH)
.............................................
50 ns
NOTE
–
Timing is representative of a 10 MHz clock. Signifi-
cantly higher speeds are attainable.
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| A6810 | DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER |
| A6810SLW | DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
| A6810EA | DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
| A6810EEP | DABiC-IV, 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS |
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