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參數資料
| 型號： | A67P9336E-3.8 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| 中文描述： | 100萬X 18，為512k × 36 LVTTL，流水線ZeBL的SRAM |
| 文件頁數： | 6/18頁 |
| 文件大?。?/td> | 249K |
| 代理商： | A67P9336E-3.8 |
A67P0618/A67P9336 Series
PRELIMINARY (September, 2004, Version 0.0)
6
AMIC Technology, Corp.
Pin Description
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50, 83
84
80
37
36
35, 34, 33, 32,
100, 99, 82, 81,
45, 46, 47, 48,
49, 50, 83, 84
44
A0
A1
A2 - A9
A11 - A18
A19
A10
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. A0 and A1 are the two lest significant bits
(LSB) of the address field and set the internal burst counter if
burst is desired.
93 (
BW1
)
94 (
BW2
)
93 (
BW1
)
94 (
BW2
)
95 (
BW3
)
96 (
BW4
)
BW1
BW2
BW3
BW4
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address, BWs are associated with
addresses and apply to subsequent data.
BW1
controls I/Oa
pins;
BW2
controls I/Ob pins;
BW3
controls I/Oc pins;
BW4
controls I/Od pins.
89
89
CLK
Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times
around the clock are rising edge.
98
98
CE
Synchronous Chip Enable : This active low input is used to
enable the device. This input is sampled only when a new
external address is loaded (ADV/
LD
LOW).
92
92
CE2
Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/
LD
LOW). This input can be used
for memory depth expansion.
97
97
CE2
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/
LD
LOW). This input can be used
for memory depth expansion.
86
86
OE
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
85
85
ADV/
LD
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
When HIGH, R/
W
is ignored. A LOW on this pin permits a
new address to be loaded at CLK rising edge.
87
87
CEN
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
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| A67P9336E-4.2 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A67P9336E-2.6 | 1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A6801 | DABiC-5 Latched Sink Drivers |
| A6801SA | DABiC-5 Latched Sink Drivers |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| A67P9336E-4.2 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 18, 512K X 36 LVTTL, Pipelined ZeBL SRAM |
| A67S | 制造商:M/A-COM Technology Solutions 功能描述:GAIN BLOCK |
| A6800 | 制造商:ALLEGRO 制造商全稱:Allegro MicroSystems 功能描述:DABiC-5 Latched Sink Drivers |
| A6800SA-T | 功能描述:IC SINK DRIVER LATCHED 14-DIP RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅動器 - 內部開關 系列:- 標準包裝:1,000 系列:- 類型:高端/低端驅動器 輸入類型:SPI 輸出數:8 導通狀態(tài)電阻:850 毫歐，1.6 歐姆 電流 - 輸出 / 通道:205mA，410mA 電流 - 峰值輸出:500mA，1A 電源電壓:9 V ~ 16 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:PG-DSO-20-45 包裝:帶卷 (TR) |
| A6800SA-T | 制造商:Allegro MicroSystems 功能描述:Driver IC Number of Drivers:4 |
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