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參數(shù)資料
| 型號(hào)： | A63P8336E-4.2F |
| 廠(chǎng)商： | AMIC Technology Corporation |
| 元件分類(lèi)： | 通用總線(xiàn)功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| 中文描述： | 256 × 36位同步高的Burst計(jì)數(shù)器和流水線(xiàn)數(shù)據(jù)輸出高速SRAM |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | A63P8336E-4.2F |
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A63P8336
PRELIMINARY
(July, 2005, Version 0.0)
11
AMIC Technology, Corp.
Timing Waveforms
CLK
ADSP
ADSC
ADDRESS
A1
A2
A3
GW,BWE
BW1-BW4
CE
(NOTE *2)
ADV
OE
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
High-Z
DOUT
t
KQLZ
(NOTE *3)
t
KQ
Single READ
t
OEHZ
t
OELZ
t
OEQ
t
KQX
t
KQ
Burst wraps around
to its initial state
t
KQHZ
BURST READ
Delselected
cycle
Burst continued with
new base address
ADV suspends
burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
(NOTE *4)
Q(A3)
(NOTE *1)
Read Timing
Notes:
*1. Q(A2) refers to output from address A2. Q(A2+1) refers to output from the internal burst address immediately
following A2.
*2. Timing for CE2 and CE2 is identical to that for CE . As shown in this diagram, when CE is LOW, CE2 is
LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
*3. Timing shown assumes that the device was not enabled before entering this sequence. OE does not cause Q to
be driven until after the rising edge of the following clock.
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| A63P8336E-2.8 | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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| A63P8336E-3.8 | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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