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參數(shù)資料
| 型號： | A63P83361E |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 256 × 36位同步計數(shù)器高的Burst SRAM的速度和流量，通過數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | A63P83361E |
A63P83361
Preliminary
256K X 36 Bit Synchronous High Speed SRAM with
Burst Counter and Flow-through Data Output
PRELIMINARY
(July, 2005, Version 0.0)
1
AMIC Technology, Corp.
Features
Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)
Single 2.5V
±
5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Three separate chip enables allow wide range of
options for CE control, address pipelining
General Description
The A63P83361 is a high-speed SRAM containing 9M
bits of bit synchronous memory, organized as 256K
words by 36 bits.
The A63P83361 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 256K X 36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A17), all data inputs (I/O
1
- I/O
36
), active LOW chip
enable (
CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables (BWE , BW1, BW2 , BW3 , BW4 ) and Global
Write (GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Industrial operating temperature range: -45
°
C to
+125
°
C for -I series
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63P83361
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| A63P83361E-6.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P83361E-6.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P83361E-7.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P83361E-7.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P83361E-8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
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