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參數(shù)資料
| 型號： | A63P83361E-8F |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 256 × 36位同步計數(shù)器高的Burst SRAM的速度和流量，通過數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | A63P83361E-8F |
A63P83361
PRELIMINARY
(July, 2005, Version 0.0)
11
AMIC Technology, Corp.
Timing Waveforms
Read Timing
Notes: 1. QA(2) refers to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
2. CE and CE2 have timing identical to CE. On this diagram, when CE is LOW, CE2 is LOW and CE2 is HIGH.
WhenCE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE does not
cause Q to be driven until after the following clock rising edge.
CLK
ADSP
ADSC
ADDRESS
A1
A2
GW,BWE
BW1-BW4
CE
(NOTE 2)
ADV
OE
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
High-Z
DOUT
(NOTE 3)
t
OEHZ
t
KQX
t
KQ
t
KQX
BURST READ
Deselect cycle
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
(NOTE *1)
t
OEQ
t
KQLZ
t
KQ
t
OELZ
Single READ
Don't Care
Undefined
A3
Q(A2+3)
Q(A3)
t
KQHZ
Deselect with CE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A63P8336E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-2.6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-2.6F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-2.8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P8336E-2.8F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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