參數(shù)資料
型號: A63P83361E-8
廠商: AMIC Technology Corporation
元件分類: 通用總線功能
英文描述: 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output
中文描述: 256 × 36位同步計數(shù)器高的Burst SRAM的速度和流量,通過數(shù)據(jù)輸出
文件頁數(shù): 10/16頁
文件大?。?/td> 262K
代理商: A63P83361E-8
A63P83361
PRELIMINARY
(July, 2005, Version 0.0)
9
AMIC Technology, Corp.
AC Characteristics
(0
°
C
T
A
70
°
C, VCC = 2.5V+5% or 2.5V-5%)
Symbol
Parameter
-6.5
-7.5
-8.5
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
T
KC
Clock Cycle Time
7.5
-
8.5
-
10
-
ns
T
KH
Clock High Time
2.5
-
2.8
-
3.0
-
ns
T
KL
Clock Low Time
2.5
-
2.8
-
3.0
-
ns
T
KQ
Clock to Output Valid
-
6.5
-
7.5
-
8.5
ns
t
KQX
Clock to Output Invalid
3.0
-
3.0
-
3.0
-
ns
t
KQLZ
Clock to Output in Low-Z
2.5
-
2.5
-
2.5
-
ns
5, 6
t
KQHZ
Clock to Output in High-Z
-
3.5
-
3.5
-
5.0
ns
5, 6
t
OEQ
OE to Output Valid
-
3.5
-
3.5
-
5.0
ns
8
t
OELZ
OE to Output in Low-Z
0
-
0
-
0
-
ns
5, 6
t
OEHZ
OE to Output in High-Z
-
3.5
-
3.5
-
5.0
ns
5, 6
Setup Times
T
AS
Address
1.5
-
2.0
-
2.0
-
ns
7, 9
t
ADSS
Address Status ( ADSC , ADSP )
1.5
-
2.0
-
2.0
-
ns
7, 9
t
ADVS
Address Advance ( ADV )
1.5
-
2.0
-
2.0
-
ns
7, 9
t
WS
Write Signals
(BW1, BW2 , BW3 , BW4 , BWE , GW )
1.5
-
2.0
-
2.0
-
ns
7, 9
T
DS
Data-in
1.5
-
1.5
-
2.0
-
ns
7, 9
t
CES
Chip Enable (CE, CE2, CE2 )
1.5
-
2.0
-
2.0
-
ns
7, 9
Hold Times
T
AH
Address
0.5
0.5
0.5
ns
7, 9
t
ADSH
Address Status ( ADSC , ADSP )
0.5
0.5
0.5
ns
7, 9
t
AAH
Address Advance ( ADV )
0.5
0.5
0.5
ns
7, 9
t
WH
Write Signal
(BW1, BW2 , BW3 ,BW4 , BWE , GW )
0.5
0.5
0.5
ns
7, 9
T
DH
Data-in
0.5
0.5
0.5
ns
7, 9
t
CEH
Chip Enable (CE, CE2, CE2 )
0.5
0.5
0.5
ns
7, 9
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