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參數(shù)資料
| 型號(hào)： | A63P83361E-7.5 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 256 × 36位同步計(jì)數(shù)器高的Burst SRAM的速度和流量，通過數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 262K |
| 代理商： | A63P83361E-7.5 |
A63P83361
PRELIMINARY
(July, 2005, Version 0.0)
13
AMIC Technology, Corp.
Timing Waveforms (continued)
Read/Write Timing
Notes: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.
2. CE2 and CE2 have timing identical to CE. On this diagram, whenCE is LOW, CE is LOW and CE2 is HIGH,
When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC , or ADV cycle is
performed.
4. Byte Write enables are decided by means of a Write truth table.
5. Back-to-back READs may be controlled by either ADSP or ADSC
CLK
ADSP
ADSC
ADDRESS
A1
A3
CE
(NOTE 2)
ADV
OE
D(A3)
D(A5)
D(A6)
High-Z
DIN
t
CEH
t
CES
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
A2
A4
A5
A6
GW,BWE,
BW1-BW4
(NOTE 3)
Q(A1)
Q(A2)
Q(A4)
Q(A4+1)
DOUT
Back-to-Back READs
Single WRITE
BURST READ
Back-to-Back
WRITEs
(NOTE 1)
t
KQ
t
OELZ
t
DH
t
DS
t
WS
t
WH
t
AS
t
AH
Q(A4+2)
Q(A4+3)
t
OEHZ
t
KQ
Don't Care
Undefined
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