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參數(shù)資料
| 型號： | A63P83361E-6.5 |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| 中文描述： | 256 × 36位同步計數(shù)器高的Burst SRAM的速度和流量，通過數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | A63P83361E-6.5 |
A63P83361
PRELIMINARY
(July, 2005, Version 0.0)
12
AMIC Technology, Corp.
Timing Waveforms (continued)
CLK
ADSP
ADSC
ADDRESS
A1
A2
A3
OE
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
High-Z
DIN
t
AH
t
AS
t
ADSH
t
ADSS
t
ADSH
t
ADSS
t
KL
t
KH
t
KC
t
ADSH
ADSS
ADSC extends t
GW
CE
(NOTE 2)
ADV
D(A1)
D(A2+1)
D(A3+2)
DOUT
BURST READ
Single WRITE
Extended BURST WRITE
t
OEHZ
t
DH
t
DS
(NOTE 3)
(NOTE 4)
ADV suspends burst
t
ADVH
t
ADVS
t
CEH
t
CES
t
WH
t
WS
BYTE WRITE signals are ignored
for first cycle when ADSP initiates burst
t
WH
t
WS
BWE,BW1-BW4
(NOTE 5)
(NOTE 1)
Don't Care
Undefined
Write Timing
Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
2. Timing for CE2 and CE2 is identical to that for CE. As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
4. ADV must be HIGH to permit a Write to the loaded address.
5. Byte Write enables are decided by means of a Write truth table.
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相關代理商/技術參數(shù) |
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| A63P83361E-7.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
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| A63P83361E-8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P83361E-8F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output |
| A63P8336E | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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