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參數(shù)資料
| 型號(hào)： | A63P0636E-3.8F |
| 廠商： | AMIC Technology Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| 中文描述： | 100萬(wàn)米鼠36位同步高的Burst計(jì)數(shù)器和流水線數(shù)據(jù)輸出高速SRAM |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | A63P0636E-3.8F |
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A63P0636
PRELIMINARY
(July, 2005, Version 0.0)
6
AMIC Technology, Corp.
Notes: 1. X = "Disregard", H = Logic High, L = Logic Low.
2. WRITE = L means:
1) Any BWx (BW1,BW2 ,BW3 , or BW4 ) and BWE are low or
2) GW is low.
3. All inputs except OE must be synchronized with setup and hold times around the rising edge (L-H) of CLK.
4. For write cycles that follow read cycles, OE must be HIGH before the input data request setup time and held
HIGH throughout the input data hold time.
5. ADSP LOW always initiates an internal Read at the L-H edge of CLK. A Write is performed by setting one or
more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. Refer to
the Write timing diagram for clarification.
Write Truth Table
Operation
GW
BWE
BW1
BW2
BW3
BW4
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte 1
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
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