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參數(shù)資料
| 型號： | A63P0636E-2.8 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| 中文描述： | 100萬米鼠36位同步高的Burst計(jì)數(shù)器和流水線數(shù)據(jù)輸出高速SRAM |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 257K |
| 代理商： | A63P0636E-2.8 |
A63P0636
Preliminary
1M X 36 Bit Synchronous High Speed SRAM with
Burst Counter and Pipelined Data Output
PRELIMINARY
(July, 2005, Version 0.0)
1
AMIC Technology, Corp.
Features
Fast
(250/227/200/166/150/133 MH
Z
)
Single +2.5V+10% or +2.5V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
General Description
The A63P0636E is a high-speed SRAM containing 36M
bits of bit synchronous memory, organized as 1024K
words by 36 bits.
The A63P0636E combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 1MX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A19), all data inputs (I/O
1
- I/O
36
), active LOW chip enable
(
CE ), two additional chip enables (CE2, CE2 ), burst
control inputs ( ADSC , ADSP , ADV ), byte write enables
( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
(GW ). Asynchronous inputs include output enable (OE ),
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
access
times:
2.6/2.8/3.2/3.5/3.8/4.2
ns
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63P0636E
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A63P0636E-2.8F | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.5 | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.5F | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.8 | ECONOLINE: RB & RA - Dual Output from a Single Input Rail- Power Sharing on Output- Industry Standard Pinout- 1kVDC & 2kVDC Isolation- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 85% |
| A63P0636E-3.8F | 1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A63P0636E-3.2 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.2F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.5F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
| A63P0636E-3.8 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output |
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