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Timing Waveforms (continued)
Write Cycle 2
(6)
(Chip Enable Controlled)
A62S7308B Series
PRELIMINARY
(March, 2001, Version 0.2)
9
AMIC Technology, Inc.
t
WC
Address
CE1
CE2
D
IN
t
DH
t
DW
(4)
(4)
t
CW5
t
AW
t
WR3
WE
D
OUT
t
WHZ7
t
WP2
t
CW5
t
AS1
Notes: 1. t
AS
is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (t
WP
) of a low
CE1
, a high CE2 and a low
WE
.
3. t
WR
is measured from the earliest of
CE1
or
WE
going high or CE2 going low to the end of the Write cycle.
4. If the
CE1
low transition or the CE2 high transition occurs simultaneously with the
WE
low transition or after
the
WE
transition, outputs remain in a high impedance state.
5. t
CW
is measured from the later of
CE1
going low or CE2 going high to the end of Write.
6.
OE
is continuously low. (
OE
= V
IL
)
7. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
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