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參數(shù)資料
| 型號(hào)： | A625308R |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32K X 8 BIT CMOS SRAM |
| 中文描述： | 32K的× 8位CMOS的SRAM |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | A625308R |
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A625308 Series
PRELIMINARY
(December, 2000, Version 0.2)
5
AMIC Technology, Inc.
AC Characteristics
(T
A
= 0
°
C to +70
°
C, VCC = 5.0V
±
10%)
Symbol
Parameter
A625308-70L/70S
Unit
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
70
-
ns
t
AA
Address Access Time
-
70
ns
t
ACE
Chip Enable Access Time
-
70
ns
t
OE
Output Enable to Output Valid
-
35
ns
t
CLZ
Chip Enable to Output in Low Z
10
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
ns
t
CHZ
Chip Disable to Output in High Z
-
25
ns
t
OHZ
Output Disable to Output in High Z
-
25
ns
t
OH
Output Hold from Address Change
5
-
ns
Write Cycle
t
WC
Write Cycle Time
70
-
ns
t
CW
Chip Enable to End of Write
60
-
ns
t
AS
Address Set up Time
0
-
ns
t
AW
Address Valid to End of Write
60
-
ns
t
WP
Write Pulse Width
50
-
ns
t
WR
Write Recovery Time
0
-
ns
t
WHZ
Write to Output in High Z
-
30
ns
t
DW
Data to Write Time Overlap
30
-
ns
t
DH
Data Hold from Write Time
0
-
ns
t
OW
Output Active from End of Write
5
-
ns
Notes: t
CHZ
, t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are not
referred to output voltage levels.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A625308R-70L | 32K X 8 BIT CMOS SRAM |
| A625308R-70S | 32K X 8 BIT CMOS SRAM |
| A625308-S | 32K X 8 BIT CMOS SRAM |
| A625308V | 32K X 8 BIT CMOS SRAM |
| A625308V-70L | 32K X 8 BIT CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A625308R-70L | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT CMOS SRAM |
| A625308R-70S | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT CMOS SRAM |
| A625308-S | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT CMOS SRAM |
| A625308V | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT CMOS SRAM |
| A625308V-70L | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:32K X 8 BIT CMOS SRAM |
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