Table 2-10 AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Min. Max. Units I
參數(shù)資料
型號： A54SX08A-FGG144I
廠商： Microsemi SoC
文件頁數(shù)： 28/108頁
文件大?。?/td> 0K
描述： IC FPGA SX 12K GATES 144-FBGA
標準包裝： 160
系列： SX-A
LAB/CLB數(shù)： 768
輸入/輸出數(shù)： 111
門數(shù)： 12000
電源電壓： 2.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 144-LBGA
供應(yīng)商設(shè)備封裝： 144-FPBGA（13x13）
SX-A Family FPGAs
2- 6
v5.3
Table 2-10 AC Specifications (3.3 V PCI Operation)
Symbol
Parameter
Condition
Min.
Max.
Units
IOH(AC)
Switching Current High
0 < VOUT ≤ 0.3VCCI
1
–12VCCI
–mA
0.3VCCI ≤ VOUT < 0.9VCCI
1
(–17.1(VCCI – VOUT))
–
mA
0.7VCCI < VOUT < VCCI
1, 2
–
–
(Test Point)
VOUT = 0.7VCC
2
––32VCCI
mA
IOL(AC)
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI
1
16VCCI
–mA
0.6VCCI > VOUT > 0.1VCCI
1
(26.7VOUT)–
mA
0.18VCCI > VOUT > 0
1, 2
–
–
(Test Point)
VOUT = 0.18VCC
2
–
38VCCI
mA
ICL
Low Clamp Current
–3 < VIN ≤ –1
–25 + (VIN + 1)/0.015
–
mA
ICH
High Clamp Current
VCCI + 4 > VIN ≥ VCCI + 1
25 + (VIN – VCCI – 1)/0.015
–
mA
slewR
Output Rise Slew Rate
0.2VCCI - 0.6VCCI load
3
14
V/ns
slewF
Output Fall Slew Rate
0.6VCCI - 0.2VCCI load
3
14
V/ns
Notes:
1. Refer to the V/I curves in Figure 2-2 on page 2-7. Switching current characteristics for REQ# and GNT# are permitted to be one half
of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#,
which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#,
which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in Figure 2-2 on page 2-7. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
Output
Buffer
1/2 in. max.
10 pF
Pin
1 k/25
Ω
1 k/25
Ω
Pin
Buffer
Output
10 pF
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX08AFGG208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
A54SX08A-FGG208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Automotive Family FPGAs
A54SX08AFGG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX-A Family FPGAs
A54SX08A-FPQ208 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:SX-A 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A54SX08A-FPQ208A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SX-A Family FPGAs
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